H.-S.P. Wong

发表

Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation

Kok Wai Wong, E. Nowak, D. Boyd, 2002, Digest. International Electron Devices Meeting,.

Monte Carlo modeling of threshold variation due to dopant fluctuations

M. Ieong, D. Frank, H.-S.P. Wong, 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation

D. Frank, H.-S.P. Wong, P. Solomon, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Simulation of stochastic doping effects in Si MOSFETs

D. Frank, H.-S.P. Wong, 2000, 7th International Workshop on Computational Electronics. Book of Abstracts. IWCE (Cat. No.00EX427).

Discrete random dopant distribution effects in nanometer-scale MOSFETs

D. Frank, H.-S.P. Wong, Y. Taur, 1998 .

Generalized scale length for two-dimensional effects in MOSFETs

D. Frank, H.-S.P. Wong, Y. Taur, 1998, IEEE Electron Device Letters.

Strained Si NMOSFETs for high performance CMOS technology

A. Grill, M. Ieong, S. Koester, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

Triple-self-aligned, planar double-gate MOSFETs: devices and circuits

J. Treichler, K. Guarini, G. Cohen, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices

E. Nowak, D. Boyd, J. Kedzierski, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel

H.-S.P. Wong, Y. Taur, K.K. Chan, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs

M. Ieong, D. Boyd, S. Koester, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Analysis of the design space available for high- kgate dielectrics in nanoscale MOSFETs

D. Frank, H.-S.P. Wong, 2000 .

Extreme scaling with ultra-thin Si channel MOSFETs

H.-S.P. Wong, Ying Zhang, Leathen Shi, 2002, Digest. International Electron Devices Meeting,.

Examination of hole mobility in ultra-thin body SOI MOSFETs

M. Ieong, W. Haensch, T. Kanarsky, 2002, Digest. International Electron Devices Meeting,.

Mobility enhancement in strained Si NMOSFETs with HfO/sub 2/ gate dielectrics

A. Mocuta, B.H. Lee, T. Kanarsky, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFET's

R.V.H. Booth, T. J. Krutsick, Marvin H. White, 1987 .

High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric

W. Haensch, H.-S.P. Wong, J. Ott, 2002, Digest. International Electron Devices Meeting,.

Self-aligned n-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate

H.-S.P. Wong, W. Haensch, P. Kozlowski, 2004, IEEE Electron Device Letters.

Strained Si CMOS (SS CMOS) technology: Opportunities and challenges

Keith A. Jenkins, Byoung Hun Lee, P. Oldiges, 2003 .

Fabrication of metal gated FinFETs through complete gate silicidation with Ni

H.-S.P. Wong, T. Kanarsky, J. Kedzierski, 2004, IEEE Transactions on Electron Devices.

Monitoring hot-carrier degradation in SOI MOSFETs by hot-carrier luminescence techniques

H.-S.P. Wong, L. Selmi, E. Sangiorgi, 1998 .

A CMOS-integrated 'ISFET-operational amplifier' chemical sensor employing differential sensing

Marvin H. White, H.-S.P. Wong, M. White, 1989 .

The Ion Sensitivity of Boron Implanted Silicon Nitride Chemical Sensors

H.-S.P. Wong, M. White, Yin Hu, 1989 .

A Guideline for Silicon Carbide MOSFET Thermal Characterization based on Source-Drain Voltage

H.-S.P. Wong, Zhebie Lu, Yi Zhang, 2022, 2023 IEEE Applied Power Electronics Conference and Exposition (APEC).

Modeling the Impact of Body-to-body Leakage in Partially-Depleted SOI CMOS Technology

M. Ieong, H.-S.P. Wong, S. Fung, 2001 .

Device scaling limits of Si MOSFETs and their application dependencies

Yuan Taur, David J. Frank, Robert H. Dennard, 2001, Proc. IEEE.

Two gates are better than one [double-gate MOSFET process]

J. Benedict, J. Treichler, H.-S.P. Wong, 2003, IEEE Circuits and Devices Magazine.

Field effect transistors-from silicon MOSFETs to carbon nanotube FETs

H.-S.P. Wong, Hon-Sum Philip Wong, 2002, 2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595).

Electron and hole mobility enhancement in strained SOI by wafer bonding

James L. Speidell, Steven A. Cordes, Steven J. Koester, 2002 .

Electrical characterization of germanium p-channel MOSFETs

H.-S.P. Wong, E.C. Jones, P. Kozlowski, 2003, IEEE Electron Device Letters.

Monte Carlo modeling of threshold variation due to dopant fluctuations

D. Frank, H.-S.P. Wong, M. Ieong, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

Extension and source/drain design for high-performance FinFET devices

Ying Zhang, David M. Fried, Meikei Ieong, 2003 .

Schottky-Barrier Carbon Nanotube Field-Effect Transistor Modeling

H. Wong, H.-S.P. Wong, T. Krishnamohan, 2007, IEEE Transactions on Electron Devices.