Ho Choi

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)

Hsien-Hsin S. Lee, Xin Zhao, Sung Kyu Lim, 2015, IEEE Transactions on Computers.

Packaging a 40-Gbps serial link using a wire-bonded plastic ball grid array

Joungho Kim, Dong Gun Kam, Ho Choi, 2006, IEEE Design & Test of Computers.

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)

Gabriel H. Loh, Dong Hyuk Woo, D. L. Lewis, 2015, IEEE Transactions on Computers.

3D-MAPS: 3D Massively parallel processor with stacked memory

Hsien-Hsin S. Lee, Xin Zhao, Sung Kyu Lim, 2012, 2012 IEEE International Solid-State Circuits Conference.