W. Lo

发表

3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)

M. Kao, Wen-Wei Shen, Yu-Min Lin, 2018, IEEE Journal of the Electron Devices Society.

Low slow-wave effect and crosstalk for low-cost ABF-coated TSVs in 3-D IC interposer

W. Lo, Yu-Jen Chang, Tai-Yu Zheng, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Monolithic 3D BEOL FinFET switch arrays using location-controlled-grain technique in voltage regulator with better FOM than 2D regulators

C. Hu, W. Yeh, W. Lo, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Cu/BCB hybrid bonding with TSV for 3D integration by using fly cutting technology

Wen-Wei Shen, Hsiang-Hung Chang, W. Lo, 2015, 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference (ICEP-IAAC).

A clamped through silicon via (TSV) interconnection for stacked chip bonding using metal cap on pad and metal column forming in via

W. Lo, Hsien-Chie Cheng, Chao-Kai Hsu, 2008, 2008 58th Electronic Components and Technology Conference.

Through-Silicon Hole Interposers for 3-D IC Integration

M. Kao, W. Lo, J. Lau, 2014, IEEE Transactions on Components, Packaging and Manufacturing Technology.

A Novel 3D Integration Scheme for Backside Illuminated CMOS Image Sensor Devices

Hsiang-Hung Chang, W. Lo, Kuan-Neng Chen, 2014, IEEE Transactions on Device and Materials Reliability.

Compact TSV-based wideband bandpass filters on 3-D IC

W. Lo, P. Chen, Shih-Hsien Wu, 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

Ultra-thin Hf0.5Zr0.5O2 Ferroelectric Tunnel Junction with High Current Density

P. Tzeng, T. Hou, W. Lo, 2021, 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

An innovative chip-to-wafer and wafer-to-wafer stacking

Wei-Chung Lo, Su-Tsai Lu, Yu-Hua Chen, 2006, 56th Electronic Components and Technology Conference 2006.

Interconnection of Flexible Electronic-Optical Circuit Board Module

Hsiang-Hung Chang, W. Lo, H. Fu, 2006, 2006 International Microsystems, Package, Assembly Conference Taiwan.

Characterization of organic multi-mode optical waveguides for the electro-optical printed circuit board (EOPCB)

Hsiang-Hung Chang, W. Lo, H. Fu, 2004 .

Reliability tests for a three dimensional chip stacking structure with through silicon via connections and low cost

W. Lo, T. Kuo, Chao-Kai Hsu, 2008, 2008 58th Electronic Components and Technology Conference.

Improvement of Nanotwinned Copper Thermal Stability for High Temperature Heterogeneous Integration

Hsiang-Hung Chang, W. Lo, O. Lee, 2021, 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Process integration and 3D chip stacking for low cost backside illuminated CMOS image sensor

Chia-Hsin Lee, Ding-Ming Kwai, Ming-Jer Kao, 2015, 2015 International Symposium on VLSI Technology, Systems and Applications.

Transient Thermal Damage Simulation for Novel Location-Controlled Grain Technique in Monolithic 3D IC

C. Hu, W. Lo, Kuan-Neng Chen, 2019, 2019 14th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).

Process-Induced Magnetic Tunnel Junction Damage and its Recovery for the Development of Spin-Orbit Torque Magnetic Random Access Memory

W. Lo, Y. Hsin, S. Sheu, 2022, SSRN Electronic Journal.

Structural design, process, and reliability of a wafer-level 3D integration scheme with Cu TSVs based on micro-bump/adhesive hybrid wafer bonding

C. K. Lee, Y. J. Huang, Y. H. Chen, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Thermal Transistor: Heat Flux Switching and Modulating

Baowen Li, Lei Wang, W. Lo, 2008, 0803.2942.

A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices

C. Lo, W. Lo, Meng-Fan Chang, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

BEOL-Compatible Multiple Metal-Ferroelectric-Metal (m-MFM) FETs Designed for Low Voltage (2.5 V), High Density, and Excellent Reliability

P. Tzeng, T. Hou, W. Lo, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

3D Scalable, Wake-up Free, and Highly Reliable FRAM Technology with Stress-Engineered HfZrOx

M. H. Lee, S. S. Sheu, H. Y. Lee, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

600V, 450A IGBT power module for 50kw electrical vehicle

Kuo-Shu Kao, Tao-Chih Chang, Wei Li, 2013, 2013 4th IEEE International Symposium on Power Electronics for Distributed Generation Systems (PEDG).

Fully 3-D symmetrical TSV monolithic transformer for RFIC

Shawn S. H. Hsu, S. S. Sheu, C. S. Lin, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices

C. Lo, W. Lo, Meng-Fan Chang, 2023, 2023 IEEE International Solid- State Circuits Conference (ISSCC).

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

Dual-phase solid-liquid interdiffusion bonding, a solution for the die attachment of WBG

Tao-Chih Chang, W. Lo, T. Chuang, 2012 .

Failure mechanism of 20 μm pitch microjoint within a chip stacking architecture

Ren-Shin Cheng, Tai-Hong Chen, John H. Lau, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

Highly Reliable, Scalable, and High-Yield HfZrOx FRAM by Barrier Layer Engineering and Post-Metal Annealing

T. Hou, W. Lo, S. Sheu, 2022, 2022 International Electron Devices Meeting (IEDM).

An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology

W. Lo, Kuan-Neng Chen, Shih-Hsien Wu, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

Thermal Performance of 3D IC Integration with Through-Silicon Via (TSV)

Sheng-Tsai Wu, John H. Lau, Heng-Chieh Chien, 2011 .

Electrical characterization and reliability investigations of Cu TSVs with wafer-level Cu/Sn-BCB hybrid bonding

W. C. Lo, Y. H. Chen, K. N. Chen, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application

Shyh-Shyuan Sheu, Kuan-Neng Chen, Yao-Jen Chang, 2012, IEEE Transactions on Device and Materials Reliability.

Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300mm Multi-Project Wafer (MPW)

Sheng-Tsai Wu, John H. Lau, T.-H. Chen, 2011 .

Thin-Wafer Handling with a Heat-Spreader Wafer for 2.5D/3D IC Integration

M. Kao, W. Lo, J. Lau, 2013 .

Reliable microjoints for chip stacking formed by solid-liquid interdiffusion (SLID) bonding

Kuo-Shu Kao, Yin-Po Hung, Ren-Shin Cheng, 2011, 2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).

Structure and Performance Co-optimization for the Development of Highly Reliable Spin-Orbit Torque Magnetic Random Access Memory

S. Z. Rahaman, W. Lo, Y. Hsin, 2023, 2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT).

Ergodicity of the Stochastic Nosé-Hoover Heat Bath

W. Lo, Baowen Li, 2010 .

Low-cost TSH (through-silicon hole) interposers for 3D IC integration

M. Kao, W. Lo, J. Lau, 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

Electrical characterization of through silicon vias (TSVs) with an on chip bus driver for 3D IC integration

J. H. Lau, M. J. Kao, S. S. Sheu, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Electrical testing of blind Through-Silicon Via (TSV) for 3D IC integration

P. Tzeng, M. Kao, W. Lo, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Ultra low-cost through-silicon holes (TSHs) interposers for 3D IC integration SiPs

Sheng-Tsai Wu, Heng-Chieh Chien, J. H. Lau, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Electrical Performance of Through-Silicon Vias (TSVs) for High-Frequency 3D IC Integration Applications

John H. Lau, Ming-Jer Kao, Shyh-Shyuan Sheu, 2012 .

Wafer Bumping and Characterizations of Fine-Pitch Lead-Free Solder Microbumps on 12" (300mm) wafer for 3D IC Integration

J. H. Lau, M. Brillhart, Li Li, 2011 .

Wafer-level 3D integration with Cu TSV and micro-bump/adhesive hybrid bonding technologies

Wei-Chung Lo, Yu-Hua Chen, Peng-Shu Chen, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

Process control of high density solder bumps by electroplating technology

W. Lo, Hsun Hu, Szu-wei Lu, 1999, Twenty Fourth IEEE/CPMT International Electronics Manufacturing Technology Symposium (Cat. No.99CH36330).

A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips

C. Lo, W. Lo, Meng-Fan Chang, 2023, IEEE Journal of Solid-State Circuits.