Yung-Fa Chou

发表

3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)

M. Kao, Wen-Wei Shen, Yu-Min Lin, 2018, IEEE Journal of the Electron Devices Society.

A Test Method for Finding Boundary Currents of 1T1R Memristor Memories

Ding-Ming Kwai, Jin-Fu Li, Yong-Xiao Chen, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

Worst-case IR-drop monitoring with 1GHz sampling rate

Shi-Yu Huang, Yung-Fa Chou, Ding-Ming Kwai, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

Process integration and 3D chip stacking for low cost backside illuminated CMOS image sensor

Chia-Hsin Lee, Ding-Ming Kwai, Ming-Jer Kao, 2015, 2015 International Symposium on VLSI Technology, Systems and Applications.

A built-in self-test scheme for 3D RAMs

Ding-Ming Kwai, Jin-Fu Li, Cheng-Wen Wu, 2012, 2012 IEEE International Test Conference.

A hybrid built-in self-test scheme for DRAMs

Ding-Ming Kwai, Jin-Fu Li, Chao-Hsun Chen, 2015, VLSI Design, Automation and Test(VLSI-DAT).

An FPGA-based test platform for analyzing data retention time distribution of DRAMs

Ding-Ming Kwai, Jin-Fu Li, Cheng-Wen Wu, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

A hybrid ECC and redundancy technique for reducing refresh power of DRAMs

Cheng-Wen Wu, Jin-Fu Li, Chih-Yen Lo, 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

A built-in self-test scheme for the post-bond test of TSVs in 3D ICs

Ding-Ming Kwai, Yu-Jen Huang, Jin-Fu Li, 2011, 29th VLSI Test Symposium.

A channel-sharable built-in self-test scheme for multi-channel DRAMs

Ding-Ming Kwai, Jin-Fu Li, Chih-Yen Lo, 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

Three-Dimensional Integrated Circuits Design for Thousand-Core Processors: From Aspect of Thermal Management

Ding-Ming Kwai, Shih-Chieh Chang, Yung-Fa Chou, 2012 .

Design and implementation of 3D-thermal test chip for exploration of package effects

Yung-Fa Chou, D. Kwai, Shih-Chieh Chang, 2011, 2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).

Realization of virtual 126-core system with thermal sensor-network using metallic thermal skeletons

Ding-Ming Kwai, Shih-Chieh Chang, Ping-Hei Chen, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

Floorplanning 1024 cores in a 3D-stacked networkon- chip with thermal-aware redistribution

Ding-Ming Kwai, Yung-Fa Chou, Chin-Chi Hsu, 2010, 2010 12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems.

Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs

Ding-Ming Kwai, Cheng-Wen Wu, Ming-Der Shieh, 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias

Ding-Ming Kwai, Cheng-Wen Wu, Yung-Fa Chou, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

CAD reference flow for 3D via-last integrated circuits

Ding-Ming Kwai, Wen Ching Wu, Yung-Fa Chou, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Temperature-aware online testing of power-delivery TSVs

Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou, 2015, 2015 International 3D Systems Integration Conference (3DIC).

Testing power-delivery TSVs

Shi-Yu Huang, Ding-Ming Kwai, Jin-Cheng Jiang, 2015, 2015 6th Asia Symposium on Quality Electronic Design (ASQED).

Is 3D integration the way out of the crossroads?

Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu, 2010, 2010 IEEE Asian Solid-State Circuits Conference.