H. Hulgaard

发表

FAST BACKTRACK-FREE PRODUCT CONFIGURATION USING A PRECOMPILED SOLUTION SPACE REPRESENTATION

R. M. Jensen, H. Andersen, T. Hadzic, 2004 .

Comparing Two Implementations of a Complete and Backtrack-Free Interactive Configurator

R. M. Jensen, H. Andersen, T. Hadzic, 2004 .

Testing Asynchronous Circuits: a Survey 1 Testing Asynchronous Circuits: a Survey

H. Hulgaard, S. Burns, Gaetano BorrielloDepartment, 1994 .

Timed Veri ation of Asyn hronous Cir uits ?

Jesper B. Møller, H. Hulgaard, Henrik Reif AndersenThe, 2002 .

Nonstochastic analysis of manufacturing system using timed-event graphs

Henrik Hulgaard, Tod Amon, H. Hulgaard, 1996 .

Difference Decision Diagrams

Henrik Reif Andersen, Henrik Hulgaard, Jesper B. Møller, 1999, CSL.

Verification of Large State/Event Systems Using Compositionality and Dependency Analysis

Kim G. Larsen, Gerd Behrmann, Henrik Reif Andersen, 1998, Formal Methods Syst. Des..

An algorithm for exact bounds on the time separation of events in concurrent systems

Gaetano Borriello, Steven M. Burns, Henrik Hulgaard, 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

Bounded Delay Timing Analysis of a Class of CSP Programs

Steven M. Burns, Henrik Hulgaard, H. Hulgaard, 1997, Formal Methods Syst. Des..

Practical verification of embedded software

Kim G. Larsen, Arne Skou, Gerd Behrmann, 2000, Computer.

Efficient Timing Analysis of a Class of Petri Nets

Steven M. Burns, Henrik Hulgaard, H. Hulgaard, 1995, CAV.

Testing asynchronous circuits: A survey

Gaetano Borriello, Steven M. Burns, Henrik Hulgaard, 1995, Integr..

Verification of Hierarchical State/Event Systems using Reusability and Compositionality

Kim G. Larsen, Gerd Behrmann, Henrik Reif Andersen, 1999, Formal Methods Syst. Des..

Symbolic timing analysis of asynchronous systems

Henrik Hulgaard, Tod Amon, H. Hulgaard, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Symbolic time separation of events

Henrik Hulgaard, Tod Amon, H. Hulgaard, 1999, Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

Symbolic model checking of timed guarded commands using difference decision diagrams

Henrik Reif Andersen, Henrik Hulgaard, Jesper B. Møller, 2002, J. Log. Algebraic Methods Program..

Fully Symbolic Model Checking of Timed Systems using Difference Decision Diagrams

Henrik Reif Andersen, Henrik Hulgaard, Jesper B. Møller, 2001, SMC@FLoC.

Timed Verification of Asynchronous Circuits

Henrik Reif Andersen, Henrik Hulgaard, Jesper B. Møller, 2002, Concurrency and Hardware Design.

On the Symbolic Verification of Timed Systems

Henrik Reif Andersen, Henrik Hulgaard, Jesper Moeller, 1999, CAV 1999.

Satisfiability checking using Boolean Expression Diagrams

H. Andersen, H. Hulgaard, P. F. Williams, 2001, International Journal on Software Tools for Technology Transfer.

Equivalence checking of hierarchical combinational circuits

Poul Frederick Williams, H. Hulgaard, H. Andersen, 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

Equivalence checking of combinational circuits using Boolean expression diagrams

Henrik Reif Andersen, Henrik Hulgaard, Poul Frederick Williams, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Boolean expression diagrams

Henrik Reif Andersen, Henrik Hulgaard, H. Andersen, 1997, Proceedings of Twelfth Annual IEEE Symposium on Logic in Computer Science.

Combinational Logic-Level Verification using Boolean Expression Diagrams

Henrik Reif Andersen, Henrik Hulgaard, Poul Frederick Williams, 1997 .

Code Generation for Embedded Systems

P. Sestoft, H. Hulgaard, A. Wąsowski, 2022 .