Yu Wang

发表

On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise

Yu Wang, Xiaoming Chen, Huazhong Yang, 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.

A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors

Meng-Fan Chang, Qi Wei, Huazhong Yang, 2017, IEEE Journal of Solid-State Circuits.

GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing

Yu Wang, Huazhong Yang, Yuan Xie, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Exploring the Granularity of Sparsity in Convolutional Neural Networks

Yu Wang, Song Han, William J. Dally, 2017, 2017 IEEE Conference on Computer Vision and Pattern Recognition Workshops (CVPRW).

ESE: Efficient Speech Recognition Engine with Compressed LSTM on FPGA pdf

Song Han, Xin Li, William J. Dally, 2016, ArXiv.

Towards Real-Time Object Detection on Embedded Systems

Yu Wang, Song Yao, Jun Yao, 2018, IEEE Transactions on Emerging Topics in Computing.

Long Live TIME: Improving Lifetime and Security for NVM-Based Training-in-Memory Systems

Xiaoming Chen, Yu Wang, Huazhong Yang, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic

Yu Wang, Meng-Fan Chang, Qi Wei, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method

Yu Wang, Yiran Chen, Yuan Xie, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Training itself: Mixed-signal training acceleration for memristor-based neural network

Yu Wang, Yiran Chen, Huazhong Yang, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

Going Deeper with Embedded FPGA Platform for Convolutional Neural Network

Yu Wang, Huazhong Yang, Jie Wang, 2016, FPGA.

A Survey of FPGA-Based Neural Network Inference Accelerator

YU WANG, Yu Wang, Huazhong Yang, 2019 .

Memristor‐Based Efficient In‐Memory Logic for Cryptologic and Arithmetic Applications

Yuchao Yang, Yu Wang, Ru Huang, 2019, Advanced Materials & Technologies.

A Hybrid CPU-GPU Accelerated Framework for Fast Mapping of High-Resolution Human Brain Connectome

Yong He, G. Gong, Yu Wang, 2013, PloS one.

An efficient technique for analysis of minimal buffer requirements of synchronous dataflow graphs with model checking

Yu Wang, Jiang Xu, Weichen Liu, 2009, CODES+ISSS '09.

JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY

Shimeng Yu, Lixue Xia, Yu Cao, 2016, Journal of Computer Science and Technology.

SEAL-lab Technical Report – No . 2015-001 ( April 29 , 2016 ) Processing-in-Memory in ReRAM-based Main Memory

Yu Wang, Jishen Zhao, Ping Chi, 2016 .

SEAL-lab Technical Report – No . 2015-001 ( November 30 , 2015 ) Processing-in-Memory in ReRAM-based Main Memory

Tao Zhang, Yu Wang, Jishen Zhao, 2015 .

PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory

Yu Wang, Jishen Zhao, Shuangchen Li, 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

FPGA Acceleration of Recurrent Neural Network Based Language Model

Yu Wang, Qinru Qiu, Chunpeng Wu, 2015, 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines.

PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory

Tao Zhang, Cong Xu, Yu Wang, 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

Evaluating Efficient Performance Estimators of Neural Architectures

Yu Wang, Huazhong Yang, Wenshuo Li, 2020, NeurIPS.

DCCB and SCC based fast circuit partition algorithm for parallel SPICE simulation

Huazhong Yang, Yu Wang, Xiaowei Zhou, 2009, 2009 IEEE 8th International Conference on ASIC.

RRAM-Based Analog Approximate Computing

Yu Wang, Yiran Chen, Huazhong Yang, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

The stochastic modeling of TiO2 memristor and its usage in neuromorphic system design

Yu Wang, Yiran Chen, Qinru Qiu, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

Memristor-based approximated computation

Yu Wang, Yiran Chen, Huazhong Yang, 2013, International Symposium on Low Power Electronics and Design (ISLPED).

Deep Gradient Compression: Reducing the Communication Bandwidth for Distributed Training pdf

William J. Dally, Yu Wang, Song Han, 2017, ICLR.

Training low bitwidth convolutional neural network on RRAM

Yu Wang, Huazhong Yang, Yi Cai, 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

Reconfigurable processor for deep learning in autonomous vehicles

Song Yao, Yi Shan, Shuang Liang, 2017 .

Binary convolutional neural network on RRAM

Yu Wang, Huazhong Yang, Lixue Xia, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

NXgraph: An efficient graph processing system on a single machine

Yu Wang, Guoliang Li, Huazhong Yang, 2015, 2016 IEEE 32nd International Conference on Data Engineering (ICDE).

GPU-Accelerated Sparse LU Factorization for Circuit Simulation with Performance Modeling

Yu Wang, Xiaoming Chen, Huazhong Yang, 2015, IEEE Transactions on Parallel and Distributed Systems.

NICSLU: An Adaptive Sparse Matrix Solver for Parallel Circuit Simulation

Yu Wang, Xiaoming Chen, Huazhong Yang, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An EScheduler-Based Data Dependence Analysis and Task Scheduling for Parallel Circuit Simulation

Wei Wu, Yu Wang, Xiaoming Chen, 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

Three-dimensional integrated circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis

Yu Wang, Yao-Wen Chang, Yuan Xie, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System

Yu Wang, Shimeng Yu, Yu Cao, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Energy efficient spiking neural network design with RRAM devices

Rong Luo, Yu Wang, Huazhong Yang, 2014, 2014 International Symposium on Integrated Circuits (ISIC).

Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA

Yu Wang, Huazhong Yang, Jincheng Yu, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

MNSIM-TIME: Performance Modeling Framework for Training-In-Memory Architectures

Yu Wang, Hanbo Sun, Kaizhong Qiu, 2021, 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS).

Black Box Search Space Profiling for Accelerator-Aware Neural Architecture Search

Yu Wang, Shulin Zeng, Hanbo Sun, 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

Communication Lower Bound in Convolution Accelerators

Yu Wang, Yinhe Han, Xiaoming Chen, 2019, 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA).

On-Chip Instruction Generation for Cross-Layer CNN Accelerator on FPGA

Yu Wang, Huazhong Yang, Jincheng Yu, 2019, 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Instruction driven cross-layer CNN accelerator with winograd transformation on FPGA

Yu Wang, Huazhong Yang, Xuefei Ning, 2017, 2017 International Conference on Field Programmable Technology (ICFPT).

Angel-Eye: A Complete Design Flow for Mapping CNN onto Customized Hardware

Song Han, Song Yao, Huazhong Yang, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Efficient 16 Boolean logic and arithmetic based on bipolar oxide memristors

Yu WANG, Rui YUAN, MA Mingyuan, 2020, Science China Information Sciences.

ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGA

Song Han, Xin Li, Song Yao, 2016, FPGA.

33.2 A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing

Meng-Fan Chang, Wei-Hao Chen, Yu Wang, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

Soft Error Mitigation for Deep Convolution Neural Network on FPGA Accelerators

Xiaoming Chen, Yu Wang, Huazhong Yang, 2020, 2020 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS).

Algorithmic Fault Detection for RRAM-based Matrix Operations

Yu Wang, Krishnendu Chakrabarty, Lixue Xia, 2020, ACM Trans. Design Autom. Electr. Syst..

FTT-NAS: Discovering Fault-Tolerant Neural Architecture

Xiaoming Chen, Yu Wang, Xuefei Ning, 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

Fault-Tolerant Training Enabled by On-Line Fault Detection for RRAM-Based Neural Computing Systems

Xuefei Ning, Krishnendu Chakrabarty, Yu Wang, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Stuck-at Fault Tolerance in RRAM Computing Systems

Yu Wang, Huazhong Yang, Yuan Xie, 2018, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Compressed CNN Training with FPGA-based Accelerator

Yu Wang, Huazhong Yang, Xuefei Ning, 2019, FPGA.

Low power Convolutional Neural Networks on a chip

Yu Wang, Song Yao, Huazhong Yang, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Energy Efficient RRAM Spiking Neural Network for Real Time Classification

Yu Wang, Huazhong Yang, Yuan Xie, 2015, ACM Great Lakes Symposium on VLSI.

A Survey of FPGA-Based Neural Network Accelerator pdf

Yu Wang, Huazhong Yang, Jincheng Yu, 2017, 1712.08934.

A heterogeneous accelerator platform for multi-subject voxel-based brain network analysis

Yu Wang, Huazhong Yang, Yong He, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Making Human Connectome Faster: GPU Acceleration of Brain Network Analysis

Yu Wang, Huazhong Yang, Yong He, 2010, 2010 IEEE 16th International Conference on Parallel and Distributed Systems.

Genetic Algorithm Based Fine-Grain Sleep Transistor Insertion Technique for Leakage Optimization

Rong Luo, Yu Wang, Huazhong Yang, 2006, ICNC.

Fault Tolerance for RRAM-Based Matrix Operations

Krishnendu Chakrabarty, Yu Wang, Lixue Xia, 2018, 2018 IEEE International Test Conference (ITC).

FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface

Narayanan Vijaykrishnan, Yu Wang, Huazhong Yang, 2020, ISLPED.

Parallel Sparse Direct Solver for Integrated Circuit Simulation

Huazhong Yang, Yu Wang, Xiaoming Chen, 2017 .

Communication Lower Bound in Convolution Accelerators

Yu Wang, Xiaoming Chen, Yinhe Han, 2019, International Symposium on High-Performance Computer Architecture.

Energy efficient neural networks for big data analytics

Rong Luo, Yu Wang, Yiran Chen, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Hu-Fu: Hardware and Software Collaborative Attack Framework Against Neural Networks

Qi Wei, Huazhong Yang, Xuefei Ning, 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

TIME: A training-in-memory architecture for memristor-based deep neural networks

Yu Wang, Huazhong Yang, Yuan Xie, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

FPMR: MapReduce framework on FPGA

Yu Wang, Bo Wang, Huazhong Yang, 2010, FPGA '10.

Attentional Separation-and-Aggregation Network for Self-supervised Depth-Pose Learning in Dynamic Scenes pdf

Yu Wang, Huazhong Yang, Jincheng Yu, 2020, CoRL.

Physical Adversarial Attack on Vehicle Detector in the Carla Simulator pdf

Yu Wang, Xuefei Ning, Huazhong Yang, 2020, ArXiv.

DSA: More Efficient Budgeted Pruning via Differentiable Sparsity Allocation

Yu Wang, Xuefei Ning, Huazhong Yang, 2020, ECCV.

MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems

Lixue Xia, Yu Cao, Yuan Xie, 2020, ACM Great Lakes Symposium on VLSI.

Exploration of Electrical and Novel Optical Chip-to-Chip Interconnects

Yu Wang, Yidong Huang, Huazhong Yang, 2014, IEEE Design & Test.

A Generic Graph-based Neural Architecture Encoding Scheme for Predictor-based NAS

Yu Wang, Xuefei Ning, Huazhong Yang, 2020, ECCV.

Enabling Secure NVM-Based in-Memory Neural Network Computing by Sparse Fast Gradient Encryption

Xiaoming Chen, Yu Wang, Yi Cai, 2020, IEEE Transactions on Computers.

ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA Architecture

Yu Wang, Huazhong Yang, Yuze Chi, 2017, FPGA.

Feature Variance Regularization: A Simple Way to Improve the Generalizability of Neural Networks

Yu Wang, Lu Tian, Yi Shan, 2020, AAAI.

Output remapping technique for critical paths soft-error rate reduction

Rong Luo, Yu Wang, Huazhong Yang, 2010, IET Comput. Digit. Tech..

Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths

Yu Wang, Huazhong Yang, Q. Ding, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

GraphSAR: a sparsity-aware processing-in-memory architecture for large-scale graph processing on ReRAMs

Yu Wang, Huazhong Yang, John Wawrzynek, 2019, ASP-DAC.

Enabling Lower-Power Charge-Domain Nonvolatile In-Memory Computing With Ferroelectric FETs

Yu Wang, Huazhong Yang, Yongpan Liu, 2021, IEEE Transactions on Circuits and Systems - II - Express Briefs.

Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation

Ku He, Rong Luo, Yu Wang, 2011, IEEE Transactions on Dependable and Secure Computing.

Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication

Yu Wang, Shimeng Yu, Yu Cao, 2015, Journal of Computer Science and Technology.

GraphSDH: A General Graph Sampling Framework with Distribution and Hierarchy

Yu Wang, Huazhong Yang, Guohao Dai, 2020, 2020 IEEE High Performance Extreme Computing Conference (HPEC).

The NBTI Impact on RF Front End in Wireless Sensor Networks

Huazhong Yang, Yu Wang, Hui Wang, 2009, 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis.

Ensemble-in-One: Learning Ensemble within Random Gated Networks for Enhanced Adversarial Robustness pdf

Yu Wang, Xuefei Ning, Yi Cai, 2021, ArXiv.

Fault Tolerance in Neuromorphic Computing Systems

Krishnendu Chakrabarty, Yu Wang, Lixue Xia, 2019, 2019 24th Asia and South Pacific Design Automation Conference (ASP-DAC).

Bidirectional Database Storage and SQL Query Exploiting RRAM-Based Process-in-Memory Structure

Huazhong Yang, Yu Wang, Yuliang Sun, 2018, ACM Trans. Storage.

New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components

Yu Wang, Narayanan Vijaykrishnan, Yu Cao, 2009, International Journal of Parallel Programming.

A framework for estimating NBTI degradation of microarchitectural components

Yu Wang, Narayanan Vijaykrishnan, Yu Cao, 2009, 2009 Asia and South Pacific Design Automation Conference.

Rescuing memristor-based computing with non-linear resistance levels

Yu Wang, Xiaoming Chen, Hui Gao, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Learning the sparsity for ReRAM: mapping and pruning sparse neural network for ReRAM based accelerator

Yuan Xie, Yu Wang, Jilan Lin, 2019, ASP-DAC.

A peripheral circuit reuse structure integrated with a retimed data flow for low power RRAM crossbar-based CNN

Yu Wang, Zili Shao, Keni Qiu, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Statistical analysis of random telegraph noise in digital circuits

Yu Wang, Yu Cao, Xiaoming Chen, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

A STT-RAM-based low-power hybrid register file for GPGPUs

Yu Wang, Xiaoming Chen, Huazhong Yang, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Low Bit-Width Convolutional Neural Network on RRAM

Yu Wang, Huazhong Yang, Yi Cai, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Enabling Secure in-Memory Neural Network Computing by Sparse Fast Gradient Encryption

Yu Wang, Xiaoming Chen, Huazhong Yang, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Long Live TIME: Improving Lifetime for Training-In-Memory Engines by Structured Gradient Sparsification

Huazhong Yang, Yu Wang, Song Han, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

From model to FPGA: Software-hardware co-design for efficient neural network acceleration

Song Han, Song Yao, Huazhong Yang, 2016, 2016 IEEE Hot Chips 28 Symposium (HCS).

Long Live TIME: Improving Lifetime for Training-In-Memory Engines by Structured Gradient Sparsification

Yu Wang, Song Han, Xiaoming Chen, 2018, Design Automation Conference.

Reliability-Aware Training and Performance Modeling for Processing-In-Memory Systems

Yu Wang, Shulin Zeng, Hanbo Sun, 2021, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).

TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks

Huazhong Yang, Yuan Xie, Ming Cheng, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Software-Hardware Codesign for Efficient Neural Network Acceleration

Yu Wang, Song Han, Song Yao, 2017, IEEE Micro.

Approximate Frequent Itemset Mining for streaming data on FPGA

Qiang Xu, Huazhong Yang, Yubin Li, 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

FPGP: Graph Processing Framework on FPGA A Case Study of Breadth-First Search

Yu Wang, Huazhong Yang, Yuze Chi, 2016, FPGA.

HyVE: Hybrid vertex-edge memory hierarchy for energy-efficient graph processing

Huazhong Yang, Yu Wang, Guohao Dai, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Efficient PageRank and SpMV Computation on AMD GPUs

Feng Yan, Yu Wang, Bo Wang, 2010, 2010 39th International Conference on Parallel Processing.

Talking with Familiar Strangers: An Empirical Study on HTTPS Context Confusion Attacks

Yu Wang, Baojun Liu, Shuang Hao, 2020, CCS.

[DL] A Survey of FPGA-based Neural Network Inference Accelerators

Yu Wang, Huazhong Yang, Kaiyuan Guo, 2019, ACM Trans. Reconfigurable Technol. Syst..

LessMine: Reducing Sample Space and Data Access for Dense Pattern Mining

Yu Wang, Huazhong Yang, Tianyu Fu, 2020, 2020 IEEE High Performance Extreme Computing Conference (HPEC).

FTT-NAS: Discovering Fault-tolerant Convolutional Neural Architecture

Yu Wang, Xuefei Ning, Guangjun Ge, 2021, ACM Trans. Design Autom. Electr. Syst..

Computation-oriented fault-tolerance schemes for RRAM computing systems

Yu Wang, Huazhong Yang, Yuan Xie, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Correction: A Hybrid CPU-GPU Accelerated Framework for Fast Mapping of High-Resolution Human Brain Connectome

Yu Wang, Huazhong Yang, Yong He, 2013, PLoS ONE.

Switched by input: Power efficient structure for RRAM-based convolutional neural network

Yu Wang, Huazhong Yang, Wenqin Huangfu, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Simultaneous fine-grain sleep transistor placement and sizing for leakage optimization

Rong Luo, Yu Wang, Huazhong Yang, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

A 462GOPs/J RRAM-based nonvolatile intelligent processor for energy harvesting IoE system featuring nonvolatile logics and processing-in-memory

Meng-Fan Chang, Huazhong Yang, Yuan Xie, 2017, 2017 Symposium on VLSI Technology.

Assessment of Circuit Optimization Techniques Under NBTI

Yu Wang, Yu Cao, Xiaoming Chen, 2013, IEEE Design & Test.

RENO: A high-efficient reconfigurable neuromorphic computing accelerator design

Hao Jiang, Yu Wang, Yiran Chen, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Spiking neural network with RRAM: Can we use it for real-world application?

Rong Luo, Yu Wang, Yiran Chen, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

An Energy-Efficient Quantized and Regularized Training Framework For Processing-In-Memory Accelerators

Yu Wang, Hanbo Sun, Xiaoming Chen, 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

Sparse LU factorization for parallel circuit simulation on GPU

Yu Wang, Xiaoming Chen, Huazhong Yang, 2012, DAC Design Automation Conference 2012.

Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators

Hao Jiang, Yu Wang, Yiran Chen, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

ICE: Inline calibration for memristor crossbar-based computing engine

Yu Wang, Yiran Chen, Huazhong Yang, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

RRAM Based Buffer Design for Energy Efficient CNN Accelerator

Yu Wang, Huazhong Yang, Xuefei Ning, 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

A universal FPGA-based floating-point matrix processor for mobile systems

Wenqiang Wang, Kaiyuan Guo, Yuchun Ma, 2014, 2014 International Conference on Field-Programmable Technology (FPT).

A General Framework for Hardware Trojan Detection in Digital Circuits by Statistical Learning Algorithms

Yu Wang, Lin Wang, Xiaoming Chen, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Pub/Sub on stream: a multi-core based message broker with QoS support

Yu Zhang, Yu Wang, Huazhong Yang, 2012, DEBS.

Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits

Rong Luo, Yu Wang, Huazhong Yang, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Large scale recurrent neural network on GPU

Yu Wang, Huazhong Yang, Jiaxing Zhang, 2014, 2014 International Joint Conference on Neural Networks (IJCNN).

RETROSPECTIVE:PRIME: A Novel Processing-in-memory Architecture for Neural Network Computation in ReRAM-based Main Memory

Yu Wang, Jishen Zhao, Ping Chi, 2023 .

BARS: Joint Search of Cell Topology and Layout for Accurate and Efficient Binary ARchitectures pdf

Yu Wang, Xuefei Ning, Huazhong Yang, 2020, ArXiv.

Towards Lower Bit Multiplication for Convolutional Neural Network Training pdf

Yu Wang, Shulin Zeng, Xuefei Ning, 2020, ArXiv.

Parametric Yield-Driven Resource Binding in High-Level Synthesis with Multi-Vth/Vdd Library and Device Sizing

Yu Wang, Yuan Xie, Yibo Chen, 2012, J. Electr. Comput. Eng..

Modeling Random Telegraph Noise as a Randomness Source and its Application in True Random Number Generation

Yu Wang, Lin Wang, Xin Li, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Modern Floorplanning with Boundary Clustering Constraint

Li Li, Yu Wang, Ning Xu, 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.

FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface

Yu Wang, Huazhong Yang, N. Vijaykrishnan, 2020, ISLPED.

MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System

Shimeng Yu, Lixue Xia, Yu Cao, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

ADAMS: Asymmetric differential STT-RAM cell structure for reliable and high-performance applications

Yu Wang, Yiran Chen, Hai Li, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Multi-Agent Vulnerability Discovery for Autonomous Driving with Hazard Arbitration Reward pdf

Yu Wang, Xuefei Ning, Huazhong Yang, 2021, ArXiv.

Sparsity-oriented sparse solver design for circuit simulation

Yu Wang, Xiaoming Chen, Huazhong Yang, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

An adaptive LU factorization algorithm for parallel circuit simulation

Yu Wang, Xiaoming Chen, Huazhong Yang, 2012, 17th Asia and South Pacific Design Automation Conference.

Overall Solver Flow

Xiaoming Chen, Yu Wang, Huazhong Yang, 2017 .

A fast parallel sparse solver for SPICE-based circuit simulators

Yu Wang, Xiaoming Chen, Huazhong Yang, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Parallel Circuit Simulation on Multi/Many-core Systems

Yu Wang, Xiaoming Chen, Huazhong Yang, 2012, 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum.

On-chip hybrid power supply system for wireless sensor nodes

Yu Wang, Huazhong Yang, Yuan Xie, 2014, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Enabling FPGAs in the cloud

Yu Zhang, Yu Wang, Kun Wang, 2014, Conf. Computing Frontiers.

EURECA: On-Chip Configuration Generation for Effective Dynamic Data Access

Yu Wang, Wayne Luk, Xinyu Niu, 2015, FPGA.

Hardware Trojan Detection in Third-Party Digital Intellectual Property Cores by Multilevel Feature Analysis

Yu Wang, Jia Wang, Qiang Xu, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect

Shimeng Yu, Yu Cao, Yu Wang, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

A Surgery of the Neural Architecture Evaluators

Yu Wang, Huazhong Yang, Wenshuo Li, 2020, ArXiv.

aw_nas: A Modularized and Extensible NAS framework pdf

Yu Wang, Xuefei Ning, Huazhong Yang, 2020, ArXiv.

CNN-based Feature-point Extraction for Real-time Visual SLAM on Embedded FPGA

Yu Wang, Chao Yu, Huazhong Yang, 2020, 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Real-Time High-Quality Stereo Vision System in FPGA

Yu Wang, Ningyi Xu, Jing Yan, 2013, IEEE transactions on circuits and systems for video technology (Print).

FPGA based memory efficient high resolution stereo vision system for video tolling

Yuchen Hao, Yu Wang, Wayne Luk, 2012, 2012 International Conference on Field-Programmable Technology.

Hardware Acceleration for Accurate Stereo Vision System using Mini-Census Adaptive Support Region

Xu Chen, Yuchen Hao, Yu Wang, 2013 .

Temperature-Aware NBTI Modeling Techniques in Digital Circuits

Rong Luo, Yu Wang, Huazhong Yang, 2009, IEICE Trans. Electron..

A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect

Ku He, Rong Luo, Yu Wang, 2007, PATMOS.

Temperature-aware NBTI modeling and the impact of input vector control on performance degradation

Ku He, Rong Luo, Yu Wang, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Modeling of PMOS NBTI Effect Considering Temperature Variation

Ku He, Rong Luo, Yu Wang, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Signal-Path-Level Dual-VT Assignment for Leakage Power Reduction

Yu Wang, Huazhong Yang, Hui Wang, 2006, J. Circuits Syst. Comput..

RALP: Reconvergence-aware layer partitioning for 3D FPGAs

Yu Wang, Wayne Luk, Jinian Bian, 2013, 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig).

Hardware computing for brain network analysis

Yu Wang, Huazhong Yang, Yi Shan, 2010, 2nd Asia Symposium on Quality Electronic Design (ASQED).