V. De

发表

Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors

J. Tschanz, S. Narendra, R. Nair, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

Dynamic-sleep transistor and body bias for active leakage power control of microprocessors

S. Borkar, S. Borkar, J. Tschanz, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

A 0.45–1V fully integrated reconfigurable switched capacitor step-down DC-DC converter with high density MIM capacitor in 22nm tri-gate CMOS

Stephen T. Kim, J. Tschanz, V. De, 2013, 2013 Symposium on VLSI Circuits.

Dual-V/sub T/ SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 /spl mu/m technology generation

K. Zhang, S. Borkar, S. Narendra, 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor

Vivek De, Eby G. Friedman, Volkan Kursun, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18 /spl mu/

K. Soumyanath, S. Borkar, V. De, 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

Scaling of stack effect and its application for leakage reduction

Anantha Chandrakasan, Vivek De, Shekhar Y. Borkar, 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control

S. Narendra, V. De, P. Hazucha, 2004, 2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551).

Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance microprocessors

J. Tschanz, S. Narendra, V. De, 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

Numerical analysis of typical STT-MTJ stacks for 1T-1R memory arrays

K. Roy, J. Tschanz, V. De, 2010, 2010 International Electron Devices Meeting.

Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs

Vivek De, Shekhar Y. Borkar, Siva G. Narendra, 2001, ISLPED '01.

Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process

K. Soumyanath, S. Borkar, J. Tschanz, 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance

Nam Sung Kim, Keith A. Bowman, Tanay Karnik, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors

S. Borkar, S. Borkar, J. Tschanz, 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage

Keith A. Bowman, Vivek De, Ali Keshavarzi, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

Tunable replica circuits and adaptive voltage-frequency techniques for dynamic voltage, temperature, and aging variation tolerance

J. Tschanz, V. De, K. Bowman, 2009, 2009 Symposium on VLSI Circuits.

Numerical analysis of domain wall propagation for dense memory arrays

K. Roy, J. Tschanz, V. De, 2011, 2011 International Electron Devices Meeting.

Highlights of the IEEE ISSCC 2014 Processors, Digital, Memory, Biomedical & Next-Generation Systems Technologies, and Imagers, MEMS, Medical & Displays Sessions

Vivek De, David Stoppa, Jonathan Chang, 2015, IEEE J. Solid State Circuits.

Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs

T. Ghani, B. Bloechel, S. Borkar, 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

Session details: Statistical optimization and manufacturability

Vivek De, Chandramouli Kashyap, Sani Nassif, 2005, DAC 2005.

Impact of body bias on alpha- and neutron-induced soft error rates of flip-flops

K. Soumyanath, J. Tschanz, T. Karnik, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

Design and optimization of low voltage high performance dual threshold CMOS circuits

K. Roy, V. De, Zhanping Chen, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Design optimizations microprocessors at low temperature

Vivek De, Siva G. Narendra, Ali Keshavarzi, 2004, Proceedings. 41st Design Automation Conference, 2004..

Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS

Andres F. Malavasi, J. Tschanz, V. De, 2019, IEEE Solid-State Circuits Letters.

Process Variation and Adaptive Design

Anantha P. Chandrakasan, Vivek De, Siva G. Narendra, 2006 .

Leakage Dependence on Input Vector

Anantha P. Chandrakasan, Vivek De, Siva G. Narendra, 2006 .

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001, Huntington Beach, California, USA, 2001

Mary Jane Irwin, Enrico Macii, Vivek De, 2001, International Symposium on Low Power Electronics and Design.

Life is CMOS: why chase the life after?

S. Borkar, V. De, G. Sery, 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

5GHz 32b integer-execution core in 130nm dual-V/sub T/ CMOS

Mircea R. Stan, Sriram R. Vangal, Vasantha Erraguntla, 2002 .

Parameter variations and impact on circuits and microarchitecture

James Tschanz, Vivek De, Shekhar Y. Borkar, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage

Vivek De, J. Tschanz, S. Narendra, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS

Timothy Mattson, Saurabh Dighe, Tiju Jacob, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Energy-Quality Scalable Integrated Circuits and Systems: Continuing Energy Scaling in the Twilight of Moore’s Law

Massimo Alioto, Andrea Marongiu, Vivek De, 2018, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit

J. Tschanz, C. Augustine, Andres F. Malavasi, 2020, 2020 IEEE Symposium on VLSI Circuits.

Design and optimization of low voltage high performance dual threshold CMOS circuits

Mark C. Johnson, Kaushik Roy, Mark Johnson, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping

Saurabh Dighe, Nitin Borkar, Kaushik Roy, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

A 2.3 nJ/Frame Voice Activity Detector-Based Audio Front-End for Context-Aware System-On-Chip Applications in 32-nm CMOS

James Tschanz, Vivek De, Arijit Raychowdhury, 2013, IEEE Journal of Solid-State Circuits.

A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance

Paolo A. Aseron, Keith A. Bowman, James Tschanz, 2011, IEEE Journal of Solid-State Circuits.

Circuit techniques for dynamic variation tolerance

Keith A. Bowman, James Tschanz, Vivek De, 2009, 2009 46th ACM/IEEE Design Automation Conference.

Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance

K.A. Bowman, J.W. Tschanz, Nam Sung Kim, 2009, IEEE Journal of Solid-State Circuits.

Design space and scalability exploration of 1T-1STT MTJ memory arrays in the presence of variability and disturbances

Arijit Raychowdhury, Tanay Karnik, Dinesh Somasekhar, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS

Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging

Paolo A. Aseron, James Tschanz, Vivek De, 2016, IEEE Journal of Solid-State Circuits.

Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor

Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, 2011, IEEE Journal of Solid-State Circuits.

A 0.26% BER, 1028 Challenge-Response Machine-Learning Resistant Strong-PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection

Sanu Mathew, Vikram Suresh, Mark Anders, 2020, 2020 IEEE Symposium on VLSI Circuits.

Design Space Exploration of Typical STT MTJ Stacks in Memory Arrays in the Presence of Variability and Disturbances

J. Tschanz, V. De, K. Roy, 2011, IEEE Transactions on Electron Devices.

A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS

Sudhir Satpathy, Vikram Suresh, Himanshu Kaul, 2021, IEEE Journal of Solid-State Circuits.

A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition

Sudhir Satpathy, Vikram Suresh, Himanshu Kaul, 2020, IEEE Journal of Solid-State Circuits.

Improved Power/EM Side-Channel Attack Resistance of 128-Bit AES Engines With Random Fast Voltage Dithering

Monodeep Kar, Saibal Mukhopadhyay, Arvind Singh, 2019, IEEE Journal of Solid-State Circuits.

Reducing Power Side-Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator

Monodeep Kar, Saibal Mukhopadhyay, Arvind Singh, 2018, IEEE Journal of Solid-State Circuits.

Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS

Sandip Kundu, Muhammad M. Khellah, Vivek De, 2019, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC).

Design and reliability challenges in nanometer technologies

Vivek De, Shekhar Y. Borkar, Tanay Karnik, 2004, Proceedings. 41st Design Automation Conference, 2004..

A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Mark Anders, 2014, IEEE Journal of Solid-State Circuits.

An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Symposium on VLSI Circuits.

A Digitally Controlled Fully Integrated Voltage Regulator With 3-D-TSV-Based On-Die Solenoid Inductor With a Planar Magnetic Core for 3-D-Stacked Die Applications in 14-nm Tri-Gate CMOS

Krishnan Ravichandran, Vivek De, Sheldon Weng, 2018, IEEE Journal of Solid-State Circuits.

A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS

Suhwan Kim, Hong Wang, Hao Luo, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO

Vivek De, Saibal Mukhopadhyay, Monodeep Kar, 2020, IEEE Journal of Solid-State Circuits.

An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS

Vikram Suresh, Himanshu Kaul, Amit Agarwal, 2019, IEEE Journal of Solid-State Circuits.

36.2 An EM/Power SCA-Resilient AES-256 with Synthesizable Signature Attenuation Using Digital-Friendly Current Source and RO-Bleed-Based Integrated Local Feedback and Global Switched-Mode Control

Vivek De, Shreyas Sen, Santosh Ghosh, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures

Sanu Mathew, Vikram Suresh, Mark Anders, 2020, 2020 IEEE Symposium on VLSI Circuits.

25.3 A 128b AES Engine with Higher Resistance to Power and Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low-Dropout Regulator

Sanu Mathew, Vivek De, Monodeep Kar, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator

Sanu Mathew, Vivek De, Monodeep Kar, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

SRAM dynamic stability estimation using MPFP and its applications

Yehea I. Ismail, Vivek De, Nam-Sung Kim, 2009, Microelectron. J..

Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ

Kaushik Roy, Vivek De, Ali Keshavarzi, 2003, IEEE Trans. Very Large Scale Integr. Syst..

A 9.0-TOPS/W Hash-Based Deep Neural Network Accelerator Enabling 128× Model Compression in 10-nm FinFET CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2020, IEEE Solid-State Circuits Letters.

An All-Digital Fully Integrated Inductive Buck Regulator With A 250-MHz Multi-Sampled Compensator and a Lightweight Auto-Tuner in 130-nm CMOS

Monodeep Kar, Saibal Mukhopadhyay, Arvind Singh, 2017, IEEE Journal of Solid-State Circuits.

A 500 MHz, 68% efficient, fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS

Vivek De, Krishnan Ravichandran, Pavan Kumar, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-/spl mu/m CMOS

S. Narendra, V. De, A.P. Chandrakasan, 2004, IEEE Journal of Solid-State Circuits.

Impact of Parameter Variations on Circuits and Microarchitecture

James Tschanz, Oguz Ergin, Antonio Gonzalez, 2006, IEEE Micro.

Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique

J. Tschanz, S. Narendra, V. De, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

8.1 A 93.8% Peak Efficiency, 5V-Input, 10A Max ILOAD Flying Capacitor Multilevel Converter in 22nm CMOS Featuring Wide Output Voltage Range and Flying Capacitor Precharging

James Tschanz, Vivek De, Krishnan Ravichandran, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

On-Chip High-Resolution Timing Characterization Circuits for Memory IPs

S. Hsu, R. Krishnamurthy, J. Tschanz, 2022, European Solid-State Circuits Conference.

25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads

James Tschanz, Charles Augustine, Vivek De, 2020, 2020 IEEE Symposium on VLSI Circuits.

Dual-VT SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 μm technology generation

Kevin Zhang, Vivek De, Shekhar Borkar, 2000, ISLPED '00.

A new technique for standby leakage reduction in high-performance circuits

Vivek De, Yibin Ye, Shekhar Beaverton Borkar, 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS

J. Tschanz, C. Augustine, Andres F. Malavasi, 2020, 2020 IEEE Symposium on VLSI Circuits.

FMAX/VMIN and noise margin impacts of aging on domino read, static write, and retention of 8T 1R1W SRAM arrays in 22nm high-k/metal-gate tri-gate CMOS

Muhammad M. Khellah, James W. Tschanz, Carlos Tokunaga, 2017, 2017 Symposium on VLSI Circuits.

Near Threshold Voltage (NTV) Computing: Computing in the Dark Silicon Era

Ram Krishnamurthy, Sriram Vangal, Vivek De, 2017, IEEE Design & Test.

Mixed-Vth (MVT) CMOS circuit design methodology for low power applications

Kaushik Roy, Vivek De, Liqiong Wei, 1999, DAC '99.

Fully Integrated Voltage Regulators with Package-Embedded Inductors for Heterogeneous 3D-TSV-Stacked System-in-Package with 22nm CMOS Active Silicon Interposer Featuring Self-Trimmed, Digitally Controlled ON-Time Discontinuous Conduction Mode (DCM) Operation

William J. Lambert, Nachiket V. Desai, J. Tschanz, 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).

A 32-A, 5-V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN nMOS Power Transistors

William J. Lambert, Nachiket V. Desai, H. Then, 2022, IEEE Journal of Solid-State Circuits.

A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer

Nachiket V. Desai, J. Tschanz, V. De, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

Peak-Current-Controlled Ganged Integrated High-Frequency Buck Voltage Regulators in 22nm CMOS for Robust Cross-Tile Current Sharing

James Tschanz, Vivek De, Xiaosen Liu, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

A Dual-Rail Hybrid Analog/Digital LDO with Dynamic Current Steering for Tunable High PSRR and High Efficiency

Xiaosen Liu, Krishnan Ravichandran, Vivek De, 2020, 2020 IEEE Symposium on VLSI Circuits.

A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response

Vivek De, Xiaosen Liu, Charles Augustine, 2020, IEEE Journal of Solid-State Circuits.

A 32A 5V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN NMOS Power Transistors

James Tschanz, Vivek De, Han Wui Then, 2021, 2021 Symposium on VLSI Circuits.

A Dual-Input, Digital Hybrid Buck-LDO System Featuring Fast Load Transient Response, Zero-Wire Current Handover & Input PDN Resonance Reduction

James Tschanz, Vivek De, Xiaosen Liu, 2021, 2021 Symposium on VLSI Circuits.

A 1S Direct-Battery-Attach Integrated Buck Voltage Regulator with 5-Stack Thin-Gate 22nm FinFET CMOS Featuring Active Voltage Balancing and Cascaded Self-Turn-ON Drivers

James Tschanz, Vivek De, Harish Krishnamurthy, 2021, 2021 Symposium on VLSI Circuits.

A Light-Load Efficient Fully Integrated Voltage Regulator in 14-nm CMOS With 2.5-nH Package-Embedded Air-Core Inductors

Xiaosen Liu, Krishnan Ravichandran, Vivek De, 2019, IEEE Journal of Solid-State Circuits.

A 0.4V∼1V 0.2A/mm2 70% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOS

Vivek De, Krishnan Ravichandran, Pavan Kumar, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

S. Narendra, V. De, S. Borkar, 2005, IEEE Journal of Solid-State Circuits.

A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS

Xiaosen Liu, Krishnan Ravichandran, Vivek De, 2018, IEEE Journal of Solid-State Circuits.

A Universal Modular Hybrid LDO With Fast Load Transient Response and Programmable PSRR in 14-nm CMOS Featuring Dynamic Clamp Strength Tuning

Vivek De, Xiaosen Liu, Christopher Schaef, 2021, IEEE Journal of Solid-State Circuits.

A Dual-Rail Hybrid Analog/Digital Low-Dropout Regulator With Dynamic Current Steering for a Tunable High PSRR and High Efficiency

Xiaosen Liu, Krishnan Ravichandran, Vivek De, 2020, IEEE Solid-State Circuits Letters.

A Sub-cm3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications

Vinayak Honkote, Tao Wang, Sriram Vangal, 2017, IEEE Journal of Solid-State Circuits.

Improving compute in-memory ECC reliability with successive correction

V. De, A. Raychowdhury, Zishen Wan, 2022, Design Automation Conference.

CIM-SECDED: A 40nm 64Kb Compute In-Memory RRAM Macro with ECC Enabling Reliable Operation

Vivek De, Arijit Raychowdhury, Carlos Tokunaga, 2021, 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Mini-LEGO: A 1.5-MHz 240-A 48-V-to-1-V CPU VRM with 8.4-mm Height for Vertical Power Delivery

V. De, J. Douglas, K. Radhakrishnan, 2023, 2023 IEEE Applied Power Electronics Conference and Exposition (APEC).

8.5 A Fully Integrated Voltage Regulator in 14nm CMOS with Package-Embedded Air-Core Inductor Featuring Self-Trimmed, Digitally Controlled Variable On-Time Discontinuous Conduction Mode Operation

James Tschanz, Vivek De, Nachiket V. Desai, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

14.7 A Modular Hybrid LDO with Fast Load-Transient Response and Programmable PSRR in 14nm CMOS Featuring Dynamic Clamp Tuning and Time-Constant Compensation

James Tschanz, Vivek De, Xiaosen Liu, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A 6 GHz, 16 Kbytes L1 cache in a 100 nm dual-V/sub T/ technology using a bitline leakage reduction (BLR) technique

M. Khellah, V. De, Yibin Ye, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

Technology and design challenges for low power and high performance [microprocessors]

Vivek De, Shekhar Y. Borkar, S. Borkar, 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

Design and optimization of dual-threshold circuits for low-voltage low-power applications

Mark C. Johnson, Kaushik Roy, Vivek De, 1999, IEEE Trans. Very Large Scale Integr. Syst..

Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS

Anantha Chandrakasan, Vivek De, Shekhar Y. Borkar, 2002, ISLPED '02.

Full-chip subthreshold leakage power prediction model for sub-0 . 18 m CMOS

Anantha Chandrakasan, Vivek De, Shekhar Borkar, 2002 .

Full-chip sub-threshold leakage power prediction model for sub-0.18 /spl mu/m CMOS

A. Chandrakasan, S. Borkar, S. Narendra, 2002, Proceedings of the International Symposium on Low Power Electronics and Design.

Active Leakage Reduction and Multi-Performance Devices

Vivek De, Siva G. Narendra, James W. Tschanz, 2006 .

A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS

J. Tschanz, S. Narendra, R. Krishnamurthy, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

Design optimizations of a high performance microprocessor using combinations of dual-V/sub T/ allocation and transistor sizing

J. Tschanz, Liqiong Wei, Yibin Ye, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

Exploiting on-chip power management for side-channel security

Sanu Mathew, Vivek De, Monodeep Kar, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Low-voltage-swing monolithic dc-dc conversion

Vivek De, Eby G. Friedman, Volkan Kursun, 2004, IEEE Transactions on Circuits and Systems II: Express Briefs.

Guest Editorial Energy-Quality Scalable Circuits and Systems for Sensing and Computing: From Approximate to Communication-Inspired and Learning-Based

Massimo Alioto, Vivek De, Andrea Marongiu, 2018, IEEE J. Emerg. Sel. Topics Circuits Syst..

Microprocessor Power Optimization Through Multi-Performance

Naoya Torii, Ali Keshavarzi, Masahiko Takenaka, 2004 .

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

Saurabh Dighe, Sriram R. Vangal, Vasantha Erraguntla, 2011, IEEE Journal of Solid-State Circuits.

Reducing the data switching activity on serial link buses

Yehea I. Ismail, Vivek De, Muhammad M. Khellah, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus

Yehea I. Ismail, Vivek De, Muhammad M. Khellah, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme

Yehea I. Ismail, Vivek De, Muhammad M. Khellah, 2007, VLSI Design.

Time-Borrowing Multi-Cycle On-Chip Interconnects for Delay Variation Tolerance

Yehea I. Ismail, Keith A. Bowman, James Tschanz, 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling

Vivek De, Farid N. Najm, Muhammad M. Khellah, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation

Vivek De, Volkan Kursun, Siva G. Narendra, 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating

James Tschanz, Vivek De, Jaydeep P. Kulkarni, 2017, IEEE Journal of Solid-State Circuits.

Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency

Paolo A. Aseron, Keith A. Bowman, James Tschanz, 2010, IEEE Custom Integrated Circuits Conference 2010.

Blindsight: Blinding EM Side-Channel Leakage using Built-In Fully Integrated Inductive Voltage Regulator pdf

Sanu Mathew, Vivek De, Raheem A. Beyah, 2018, ArXiv.

Comparative Analysis of Conventional and Statistical Design Techniques

Keith A. Bowman, James Tschanz, Vivek De, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits

Vivek De, A. Chatterjee, P. Pant, 1998, IEEE Trans. Very Large Scale Integr. Syst..