D. Bertozzi

发表

Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip

Davide Bertozzi, María Engracia Gómez, Francisco Gilabert Villamón, 2010, 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip.

NoC synthesis flow for customized domain specific multiprocessor systems-on-chip

Luca Benini, Srinivasan Murali, Giovanni De Micheli, 2005, IEEE Transactions on Parallel and Distributed Systems.

Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System

Davide Bertozzi, Marta Ortín-Obón, Luca Ramini, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Exploring Communication Protocols for Optical Networks-on-Chip based on Ring Topologies

D. Bertozzi, L. Ramini, Mahdi Tala, 2014, 2014 Asia Communications and Photonics Conference (ACP).

Special Issue on Networks-on-Chip Again on the Rise: From Emerging Applications to Emerging Technologies.

José L. Abellán, M. Nikdast, D. Bertozzi, 2021, Micromachines.

[Article] Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers Original Citation:

D. Bertozzi, P. Olivo, P. Torino, 2015 .

Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs

Luca Benini, Davide Bertozzi, José L. Abellán, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Network on Chip Architectures

José Flich Cardo, N. E. Jerger, C. Teuscher, 2008 .

A synthesis oriented design library for Network On Chip

Luca Benini, Federico Angiolini, Paolo Meloni, 2005 .

Minisymposium - Network-on-ChipNetworks on Chips: A Synthesis Perspective

Federico Angiolini, Paolo Meloni, Davide Bertozzi, 2006 .

A Placement and Routing Algorithm for Optical Networks-on-Chip

Ulf Schlichtmann, Davide Bertozzi, Luca Ramini, 2014 .

Fifth International Workshop on Interconnection Network Architecture : On-Chip, Multi-Chip (INA-OCMC 2011)

Daniele Ludovici, Davide Bertozzi, Jose Flich, 2011 .

The Industrial Perspective

Davide Bertozzi, Jose Flich, D. Bertozzi, 2010 .

Euro-Par 2013 Parallel Processing

Torsten Hoefler, Davide Bertozzi, Olav Lysne, 2013, Lecture Notes in Computer Science.

Editorial

Davide Bertozzi, Giorgos Dimitrakopoulos, Sören Sonntag, 2014, Des. Autom. Embed. Syst..

An Asynchronous Soft Macro for Ultra-Low Power Communication in Neuromorphic Computing

D. Bertozzi, S. Nowick, K. Bhardwaj, 2022, 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS).

The Challenge of Classification Confidence Estimation in Dynamically-Adaptive Neural Networks

José L. Abellán, D. Bertozzi, M. Favalli, 2021, SAMOS.

On-chip wireless interconnection through reconfigurable optical phased arrays

G. Bellanca, D. Bertozzi, F. Fuschini, 2022, 2022 Italian Conference on Optics and Photonics (ICOP).

State-of-the-Art SoC Communication Architectures

Luca Benini, Davide Bertozzi, Marisa López-Vallejo, 2005, Embedded Systems Handbook.

Battery Lifetime Optimization for Energy-Aware Circuits

Luca Benini, Davide Bertozzi, L. Benini, 2018, Low-Power Electronics Design.

Networks-on-Chip: an Interconnect Fabric for Multiprocessor Systems-on-Chip

Luca Benini, Giovanni De Micheli, Davide Bertozzi, 2009, Embedded Systems Design and Verification.

Network-on-Chip Design for Gigascale Systems-on-Chip

Luca Benini, Giovanni De Micheli, Davide Bertozzi, 2005, Embedded Systems Handbook.

SoC Communication Architectures: From Interconnection Buses to Packet-Switched NoCs

Luca Benini, Davide Bertozzi, Marisa López-Vallejo, 2018, Embedded Systems Design and Verification.

Tight Integration of GALS Interfaces into the NoC Architecture

Luca Benini, Alessandro Strano, Davide Bertozzi, 2009 .

PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer

Anja von Beuningen, Ulf Schlichtmann, D. Bertozzi, 2016, ACM J. Emerg. Technol. Comput. Syst..

Transport protocol optimization for energy efficient wireless embedded systems

Luca Benini, Srivaths Ravi, Anand Raghunathan, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems

Davide Bertozzi, Gabriele Miorandi, Steven M. Nowick, 2021, IEEE Micro.

Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow

Davide Bertozzi, Gabriele Miorandi, Steven M. Nowick, 2017, 2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC).

Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems

Davide Bertozzi, Gabriele Miorandi, Marco Balboni, 2016, AISTECS '16.

Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline

Davide Bertozzi, Sandro Bartolini, Luca Ramini, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Abstract modelling of switching elements for optical networks-on-chip with technology platform awareness

Davide Bertozzi, Luca Ramini, Gaetano Bellanca, 2011, INA-OCMC '11.

A built-in self-testing framework for asynchronous bundled-data NoC switches resilient to delay variations

Davide Bertozzi, Gabriele Miorandi, Michele Favalli, 2016, 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS).

A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems

Davide Bertozzi, Steven M. Nowick, Alberto Ghiribaldi, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Architecture design principles for the integration of synchronization interfaces into network-on-chip switches

Daniele Ludovici, Alessandro Strano, Davide Bertozzi, 2009, 2009 2nd International Workshop on Network on Chip Architectures.

Correlating Power Efficiency and Lifetime to Programming Strategies in RRAM-Based FPGAs

Piero Olivo, Davide Bertozzi, Cristian Zambelli, 2018, 2018 New Generation of CAS (NGCAS).

Error control schemes for on-chip communication links: the energy-reliability tradeoff

Luca Benini, Giovanni De Micheli, Davide Bertozzi, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Bottom-Up Abstract Modelling of Optical Networks-on-Chip: From Physical to Architectural Layer

Davide Bertozzi, Luca Ramini, Gaetano Bellanca, 2012 .

Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers

Paolo Prinetto, Piero Olivo, Davide Bertozzi, 2015, ACM Trans. Embed. Comput. Syst..

FLARES: An Aging Aware Algorithm to Autonomously Adapt the Error Correction Capability in NAND Flash Memories

Paolo Prinetto, Piero Olivo, Davide Bertozzi, 2014, ACM Trans. Archit. Code Optim..

The fast evolving landscape of on-chip communication

Davide Bertozzi, Giorgos Dimitrakopoulos, Sören Sonntag, 2015, Des. Autom. Embed. Syst..

Analyzing on-chip communication in a MPSoC environment

Luca Benini, Federico Angiolini, Davide Bertozzi, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Performance Analysis of Arbitration Policies for SoC Communication Architectures

Luca Benini, Francesco Poletti, Davide Bertozzi, 2003, Des. Autom. Embed. Syst..

Guided Participatory Research on Parallel Computer Architectures for K-12 Students Through a Narrative Approach

Davide Bertozzi, Luigina Mortari, Federico Corni, 2014, CSEDU.

Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous Arbiters

Davide Bertozzi, Gabriele Miorandi, Steven M. Nowick, 2015, 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems.

Exploiting structural redundancy of SIMD accelerators for their built-in self-testing/diagnosis and reconfiguration

Alessandro Strano, Davide Bertozzi, Sami Yehia, 2011, ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors.

Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture

Michele Favalli, Daniele Ludovici, Alessandro Strano, 2011, 2011 Design, Automation & Test in Europe.

Xpipes: a network-on-chip architecture for gigascale systems-on-chip

L. Benini, D. Bertozzi, L. Benini, 2004, IEEE Circuits and Systems Magazine.

Legacy SystemC co-simulation of multi-processor systems-on-chip

Luca Benini, Massimo Poncino, Davide Bertozzi, 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

SSDExplorer: A Virtual Platform for Performance/Reliability-Oriented Fine-Grained Design Space Exploration of Solid State Drives

Paolo Prinetto, Piero Olivo, Davide Bertozzi, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Network-on-chip architectures and design methods

Luca Benini, Davide Bertozzi, L. Benini, 2005 .

Network on Chip Architectures

Natalie D. Enright Jerger, José Flich Cardo, C. Teuscher, 2008 .

Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming

Luca Benini, Davide Bertozzi, Michela Milano, 2008, ICLP.

Capturing the sensitivity of optical network quality metrics to its network interface parameters

Davide Bertozzi, Marta Ortín-Obón, Luca Ramini, 2014, Concurr. Comput. Pract. Exp..

A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip

Davide Bertozzi, Marta Ortín-Obón, Luca Ramini, 2014, GLSVLSI '14.

Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs

Luca Benini, Davide Bertozzi, Luca Giovannini, 2003, 2012 IEEE 30th International Conference on Computer Design (ICCD).

Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor SoCs

Luca Benini, Davide Bertozzi, Luca Giovannini, 2003, Proceedings 21st International Conference on Computer Design.

Network Interface Sharing Techniques for Area Optimized NoC Architectures

Davide Bertozzi, Alberto Ferrante, Simone Medardoni, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

A high-efficiency wind-flow energy harvester using micro turbine

L Benini, D Carli, D Brunelli, 2010, SPEEDAM 2010.

Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support

Luca Benini, Paul Marchal, Massimo Poncino, 2007, IEEE Transactions on Computers.

Supporting Task Migration in Multi-Processor Systems-on-Chip: A Feasibility Study

Davide Bertozzi, Andrea Acquaviva, Antonio Poggiali, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Allocation and Scheduling for MPSoCs via decomposition and no-good generation

Luca Benini, Davide Bertozzi, Michela Milano, 2005, IJCAI.

Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems

Federico Silla, José Duato, Davide Bertozzi, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories

Paolo Prinetto, Piero Olivo, Davide Bertozzi, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework

Luca Benini, Pedro López, José Duato, 2008, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008).

Logic programming approaches for routing fault-free and maximally parallel wavelength-routed optical networks-on-chip (Application paper) pdf

Marco Gavanelli, Davide Bertozzi, Maddalena Nonato, 2017, Theory and Practice of Logic Programming.

Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout Constraints

Luca P. Carloni, Davide Bertozzi, Luca Ramini, 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints

Pedro López, Daniele Ludovici, Davide Bertozzi, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints

Luca Benini, Daniele Ludovici, Davide Bertozzi, 2009, 2009 International Conference on Complex, Intelligent and Software Intensive Systems.

Energy-efficient and reliable low-swing signaling for on-chip buses based on redundant coding

Luca Benini, Bruno Riccò, Davide Bertozzi, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Low power error resilient encoding for on-chip data buses

Luca Benini, Giovanni De Micheli, Davide Bertozzi, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Energy-Efficient Network-On-Chip Design

Luca Benini, Giovanni De Micheli, Davide Bertozzi, 2004, Ultra Low-Power Electronics and Design.

Energy-Reliability trade-Off for NoCs

Luca Benini, Giovanni De Micheli, Davide Bertozzi, 2003, Networks on Chip.

The fast evolving landscape of on-chip communication

D. Bertozzi, J. Flich, G. Dimitrakopoulos, 2014, Design Automation for Embedded Systems.

4 × 4 Integrated Switches Based on On-Chip Wireless Connection through Optical Phased Arrays

G. Bellanca, D. Bertozzi, F. Fuschini, 2023, Photonics.

SystemC Cosimulation and Emulation of Multiprocessor SoC Designs

Luca Benini, Massimo Poncino, Davide Bertozzi, 2003, Computer.