R. Kirisawa

An experimental 4 Mb CMOS EEPROM with a NAND structured cell

Y. Itoh, M. Momodomi, R. Shirota, 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

A 2.3 mu m/sup 2/ memory cell structure for 16 Mb NAND EEPROMs

Y. Itoh, M. Momodomi, R. Shirota, 1990, International Technical Digest on Electron Devices.

A reliable bi-polarity write/erase technology in flash EEPROMs

Tetsuo Endoh, Fujio Masuoka, Seiichi Aritome, 1990, International Technical Digest on Electron Devices.

A non-volatile programmable semiconductor memory device

Fujio Masuoka, Riichiro Shirota, Yoshihisa Iwata, 1988 .

An accurate model of subbreakdown due to band-to-band tunneling and some applications

Tetsuo Endoh, S. Inoue, Fujio Masuoka, 1988 .

An accurate model of subbreakdown due to band-to-band tunneling and its application

S. Inoue, R. Kirisawa, F. Masuoka, 1988, Technical Digest., International Electron Devices Meeting.

Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices

Y. Iwata, Li Zhang, A. Nitayama, 2006, 2009 Symposium on VLSI Technology.

Optimal device structure for Pipe-shaped BiCS Flash memory for ultra high density storage device with excellent performance and reliability

Takashi Maeda, Akihiro Nitayama, Yoshihisa Iwata, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Electrically erasable and programmable, nichtfluechtiges storage system with write-verify-setter using two reference level

Tetsuo Endoh, Kazunori Ohuchi, Riichiro Shirota, 1992 .

A non-volatile semiconductor memory device and programming method for a nonvolatile semiconductor memory device

Tetsuo Endoh, Riichiro Shirota, Kazunori Ohuchi, 1992 .