S. Atsumi

Comparison of current flash EEPROM erasing methods: stability and how to control

K. Yoshikawa, S. Yamada, J. Miyamoto, 1992, 1992 International Technical Digest on Electron Devices Meeting.

A CMOS bandgap reference circuit with sub-1-V operation

K. Sakui, S. Atsumi, T. Tanzawa, 1999 .

A CMOS band-gap reference circuit with sub 1 V operation

Hitoshi Shiga, Toru Tanzawa, Koji Sakui, 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

A 44 mm/sup 2/ 4-bank 8-word page read 64 Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller

H. Watanabe, Y. Takano, S. Atsumi, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

A 3.3 V-only 16 Mb flash memory with row-decoding scheme

Y. Iyama, A. Umezawa, S. Atsumi, 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

A 5 V-only 0.6 mu m flash EEPROM with row decoder scheme in triple-well structure

S. Yamada, Sumio Tanaka, Akira Umezawa, 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme

H. Watanabe, S. Yamada, Y. Takano, 2000, IEEE Journal of Solid-State Circuits.

A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure

S. Yamada, Sumio Tanaka, Akira Umezawa, 1992 .

A self-consistent pseudo-two-dimensional model for hot-electron current in MOST' s

S. Atsumi, S. Tanaka, K. Yoshikawa, 1986, IEEE Transactions on Electron Devices.