G. Varatkar

Traffic analysis for on-chip networks design of multimedia applications

R. Marculescu, G. Varatkar, 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

Modeling and Synthesis of On-chip Dynamic Multimedia Traffic

R. Marculescu, G. Varatkar, 2002 .

Communication-aware task scheduling and voltage selection for total systems energy minimization

R. Marculescu, G. Varatkar, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

With Shared Microexponents, A Little Shifting Goes a Long Way

Eric S. Chung, Zhaoxia Deng, Jongsoo Park, 2023, ISCA.

Error-Resilient Motion Estimation Architecture

Naresh R. Shanbhag, Girish Varatkar, Naresh R Shanbhag, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Energy-efficient Motion Estimation using Error-Tolerance

Naresh R. Shanbhag, Girish Varatkar, Naresh R Shanbhag, 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

On-chip traffic modeling and synthesis for MPEG-2 video applications

Radu Marculescu, Girish Varatkar, R. Marculescu, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.