K. Ishibashi

发表

An alpha -immune, 2-V supply voltage SRAM using a polysilicon PMOS load cell

K. Ishibashi, T. Yamanaka, K. Shimohigashi, 1990 .

0.5 V asymmetric three-Tr. cell (ATC) DRAM using 90nm generic CMOS logic process

Y. Itoh, K. Ishibashi, M. Ichihashi, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

16.7 fA/cell tunnel-leakage-suppressed 16 Mb SRAM for handling cosmic-ray-induced multi-errors

K. Ishibashi, E. Ibe, K. Osada, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

Low power and reliable SRAM memory cell and array design

Kenichi Osada, Koichiro Ishibashi, K. Ishibashi, 2011 .

Universal-Vdd 0.65-2.0V 32 kB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric cell

K. Ishibashi, S. Ikeda, K. Osada, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

Adaptive Threshold-Voltage CMOS with Forward Bias

K. Ishibashi, G. Ono, M. Miyazaki, 2000 .

16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors

K. Ishibashi, E. Ibe, K. Osada, 2003, IEEE J. Solid State Circuits.

Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation

K. Ishibashi, T. Iwamatsu, T. Hiramoto, 2013, 2013 IEEE International Electron Devices Meeting.

An 8-mW, 8-kB Cache Memory Using an Automatic-Power-Save Architecture for Low Power RISC Microprocessors (Special Issue on low-Power LSI Technologies)

Hideo Maejima, Koichiro Ishibashi, Yasuhisa Shimazaki, 1996 .

First Experimental Confirmation of Transient Effect on Super Steep SS “PN-Body Tied SOI FET” with Pulse Measurements

J. Ida, K. Ishibashi, Y. Arai, 2019, 2019 Electron Devices Technology and Manufacturing Conference (EDTM).

Diode Characteristics of a Super-Steep Subthreshold Slope PN-Body Tied SOI-FET for Energy Harvesting Applications

K. Itoh, J. Ida, K. Ishibashi, 2018, IEEE Journal of the Electron Devices Society.

FA 13.1: A 1V TFT-Load SRAM Using a Two-step Word-Voltage Method

K. Ishibashi, T. Yamanaka, K. Sasaki, 1990 .

High Accuracy Heartbeat Detection from CW-Doppler Radar Using Singular Value Decomposition and Matched Filter

Guanghao Sun, Koichiro Ishibashi, Han Trong Thanh, 2021, Sensors.

Small-Scale Depthwise Separable Convolutional Neural Networks for Bacteria Classification

K. Ishibashi, Duc-Tho Mai, 2021, Electronics.

Precise Heart Rate Measurement Using Non-contact Doppler Radar Assisted by Machine-Learning-Based Sleep Posture Estimation

Guanghao Sun, Koichiro Ishibashi, Kotaro Higashi, 2019, 2019 41st Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

Non-contact acquisition of respiration and heart rates using Doppler radar with time domain peak-detection algorithm

Guanghao Sun, Koichiro Ishibashi, Xiaofeng Yang, 2017, 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

Dengue Fever Screening Using Vital Signs by Contactless Microwave Radar and Machine Learning

Guanghao Sun, Koichiro Ishibashi, Xiaofeng Yang, 2019, 2019 IEEE Sensors Applications Symposium (SAS).

Wireless and Low-Power Water Quality Monitoring Beat Sensors For Agri and Acqua-Culture IoT Applications

Koichiro Ishibashi, Ryohei Takitoge, Duangchak Manyvone, 2018, 2018 15th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON).

Machine learning based classification model for screening of infected patients using vital signs

Koichiro Ishibashi, Trong Tuan Do, Yuki Iwata, 2021 .

A 361nA thermal run-away immune VBB generator using dynamic substrate controlled charge pump for ultra low sleep current logic on 65nm SOTB

Nobuyuki Sugii, Koichiro Ishibashi, Shiro Kamohara, 2014, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

K. Ishibashi, M. Yabuuchi, H. Makino, 2007, IEEE Journal of Solid-State Circuits.

A 1.36 μW 312–315 MHz synchronized-OOK receiver for wireless sensor networks using 65 nm SOTB CMOS technology

Nobuyuki Sugii, Koichiro Ishibashi, Minh-Thien Hoang, 2016 .

Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era

Hideharu Amano, Kazutoshi Kobayashi, Kimiyoshi Usami, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Hideharu Amano, Duc-Hung Le, Cong-Kha Pham, 2014, 2014 IEEE COOL Chips XVII.

Dengue Fever Detecting System Using Peak-detection of Data from Contactless Doppler Radar

Guanghao Sun, Koichiro Ishibashi, Xiaofeng Yang, 2018, 2018 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

Deep Learning Approach for Classifying Bacteria types using Morphology of Bacterial Colony

K. Ishibashi, G. Sun, Nguyen Thi Hoa, 2022, 2022 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC).

Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoT Applications

K. Ishibashi, Trong-Thuc Hoang, C. Pham, 2022, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications

Trong-Thuc Hoang, Cong-Kha Pham, Koichiro Ishibashi, 2021, 2021 18th International SoC Design Conference (ISOCC).

Visualisation of epidemiological map using an Internet of Things infectious disease surveillance platform

Pham Thanh Hiep, Guanghao Sun, Takemi Matsui, 2020, Critical Care.

A non-contact infection screening system using medical radar and Linux-embedded FPGA: Implementation and preliminary validation

Guanghao Sun, Koichiro Ishibashi, Cuong V. Nguyen, 2019, Informatics in Medicine Unlocked.

7.6 µW Ambient Energy Harvesting Rectenna from LTE Mobile phone Signal for IoT Applications

Koichiro Ishibashi, Thuy-Linh Nguyen, Yasuo Sato, 2020, 2020 International Conference on Advanced Technologies for Communications (ATC).

Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell

Kenichi Osada, Kenichi Kuroda, Masood Khan, 2001, IEEE J. Solid State Circuits.

A 18 /spl mu/A-standby-current 1.8 V 200 MHz microprocessor with self substrate-biased data-retention mode

H. Mizuno, K. Shiozawa, K. Uchiyama, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

Short time cardio-vascular pulses estimation for dengue fever screening via continuous-wave Doppler radar using empirical mode decomposition and continuous wavelet transform

Guanghao Sun, Koichiro Ishibashi, Ha Manh Luu, 2021, Biomed. Signal Process. Control..

A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process

Kazumasa Yanagisawa, Koichiro Ishibashi, Yasuto Igarashi, 2011, IEEE Asian Solid-State Circuits Conference 2011.

A 300 MHz 4-Mb wave-pipeline CMOS SRAM using a multi-phase PLL

K. Ishibashi, M. Minami, K. Komiyaji, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs

K. Ishibashi, H. Okada, T. Tsukada, 2004, IEEE Journal of Solid-State Circuits.

A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die

Koji Nii, Yuji Oda, Koichiro Ishibashi, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme

K. Ishibashi, M. Yamaoka, K. Osada, 2004, IEEE Journal of Solid-State Circuits.