Vassilis Paliouras

发表

Signal activity and power consumption reduction using the logarithmic number system

T. Stouraitis, V. Paliouras, T. Stouraitis, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

High-radix residue arithmetic bases for low-power DSP systems

Vassilis Paliouras, I. Kouretas, 2009, 2009 16th International Conference on Digital Signal Processing.

Low power convolvers using the Polynomial Residue Number System

T. Stouraitis, A. Skavantzos, Vassilis Paliouras, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

A High-performance RNS LSTM block

T. Stouraitis, Vassilis Paliouras, H. Saleh, 2022, 2022 IEEE International Symposium on Circuits and Systems (ISCAS).

High-radix modulo multipliers and adders

Vassilis Paliouras, I. Kouretas, 2002 .

A Low Complexity-High Throughput QC-LDPC Encoder

Vassilis Paliouras, Ahmed Mahdi, Vassilis Paliouras, 2014, IEEE Transactions on Signal Processing.

Optimal Logarithmic Representation in Terms of SNR Behavior

Vassilis Paliouras, Panagiotis D. Vouzis, Vassilis Paliouras, 2004, PATMOS.

Hardware aspects of Long Short Term Memory

Vassilis Paliouras, Ioannis Kouretas, Vassilis Paliouras, 2018, 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Sum Propagate Adders

Vassilis Paliouras, Giorgos Dimitrakopoulos, Kleanthis Papachatzopoulos, 2021, IEEE Transactions on Emerging Topics in Computing.

A novel architecture and a systematic graph-based optimization methodology for modulo multiplication

Vassilis Paliouras, Giorgos Dimitrakopoulos, Vassilis Paliouras, 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

Application-Specific Low-Power Multipliers

Vassilis Paliouras, Panagiotis Sakellariou, Vassilis Paliouras, 2016, IEEE Transactions on Computers.

Low-Power Saturated Arithmetic and its Application in VLSI Architectures for OFDM Modems

Vassilis Paliouras, Konstantina Karagianni, Theodoros Giannopoulos, 2006, 2006 IEEE Workshop on Signal Processing Systems Design and Implementation.

Low-Power Aspects of Nonlinear Signal Processing

Vassilis Paliouras, Konstantina Karagianni, Vassilis Paliouras, 2005, PATMOS.

Graph-based optimization for a CSD-enhanced RNS multiplier

Vassilis Paliouras, Giorgos Dimitrakopoulos, Vassilis Paliouras, 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

Multi-voltage low power convolvers using the polynomial residue number system

Vassilis Paliouras, Thanos Stouraitis, Alexander Skavantzos, 2002, GLSVLSI '02.

VLSI architectures for blind equalization based on fractional-order statistics

Vassilis Paliouras, Thanos Stouraitis, Panagiotis Tsakalides, 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

Logarithmic Number System for Low-Power Arithmetic

Vassilis Paliouras, Thanos Stouraitis, T. Stouraitis, 2000, PATMOS.

Low-Power Maximum Magnitude Computation for PAPR Reduction in OFDM Transmitters

Vassilis Paliouras, Theodoros Giannopoulos, Vassilis Paliouras, 2006, PATMOS.

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Vassilis Paliouras, Diederik Verkest, Johan Vounckx, 2005, Lecture Notes in Computer Science.

On the Design of Two-Level Pipelined Processor Arrays

Vassilis Paliouras, Thanos Stouraitis, Dimitrios Soudris, 1993 .

A Reconfigurable LDPC Decoder Optimized for 802.11n/ac Applications

Vassilis Paliouras, Ioannis Tsatsaragkos, Vassilis Paliouras, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On the Encoding Complexity of Quasi-Cyclic LDPC Codes

Vassilis Paliouras, Ahmed Mahdi, Vassilis Paliouras, 2015, IEEE Transactions on Signal Processing.

Relationship among BER, power consumption and PAPR

Vassilis Paliouras, Theodoros Giannopoulos, Vassilis Paliouras, 2008, 2008 3rd International Symposium on Wireless Pervasive Computing.

A Low-Complexity PTS-based PAPR Reduction Technique for OFDM Signals without Transmission of Side Information

Vassilis Paliouras, Theodoros Giannopoulos, Vassilis Paliouras, 2006, 2006 IEEE Workshop on Signal Processing Systems Design and Implementation.

Novel efficient weighting factors for PTS-based PAPR reduction in low-power OFDM transmitters

Vassilis Paliouras, Theodoros Giannopoulos, Vassilis Paliouras, 2006, 2006 14th European Signal Processing Conference.

One-Hot Residue Logarithmic Number Systems

Vassilis Paliouras, Mark G. Arnold, Ioannis Kouretas, 2019, 2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS).

Under- and Overflow Detection in the Residue Logarithmic Number System

Vassilis Paliouras, John Cowles, Ioannis Kouretas, 2019, 2019 IEEE 26th Symposium on Computer Arithmetic (ARITH).

A Residue Logarithmic Number System ALU using interpolation and cotransformation

Vassilis Paliouras, Mark G. Arnold, Ioannis Kouretas, 2011, ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors.

RNS multi-voltage low-power multiply-add unit

Vassilis Paliouras, Ioannis Kouretas, Vassilis Paliouras, 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

Residue Arithmetic for Designing Low-Power Multiply-Add Units

Vassilis Paliouras, Ioannis Kouretas, Vassilis Paliouras, 2010, PATMOS.

Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication

Vassilis Paliouras, Ioannis Kouretas, Vassilis Paliouras, 2009, PATMOS.

High-radix redundant circuits for RNS modulo r/sup n/ - 1, r/sup n/, or r/sup n/ + 1

Vassilis Paliouras, Ioannis Kouretas, Vassilis Paliouras, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Considering the alternatives in low-power design

Vassilis Paliouras, Thanos Stouraitis, T. Stouraitis, 2001 .

High-radix residue number system forward and inverse converters

Vassilis Paliouras, Thanos Stouraitis, T. Stouraitis, 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

A low-complexity RNS multiplier

Vassilis Paliouras, Thanos Stouraitis, K. Karagianni, 2000, 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528).

Novel high-radix residue number system architectures

Vassilis Paliouras, Thanos Stouraitis, T. Stouraitis, 2000 .

Multifunction architectures for RNS processors

Vassilis Paliouras, Thanos Stouraitis, T. Stouraitis, 1999 .

Systematic design of multi-modulus/multi-function Residue Number System processors

Vassilis Paliouras, Thanos Stouraitis, T. Stouraitis, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Computer Arithmetic Techniques for Low-Power Systems

Vassilis Paliouras, Thanos Stouraitis, T. Stouraitis, 2002 .

Employing Alternative Number Systems to Reduce Power Dissipation in Portable Devices and High-Performance Systems

T. Stouraitis, V. Paliouras, T. Stouraitis, 2001 .

Low-power properties of the logarithmic number system

Vassilis Paliouras, Thanos Stouraitis, T. Stouraitis, 2001, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001.

A Low-Latency Syndrome-based Deep Learning Decoder Architecture and its FPGA Implementation

Vassilis Paliouras, E. Kavvousanos, 2022, 2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST).

Logarithmic number system for deep learning

Vassilis Paliouras, Ioannis Kouretas, Vassilis Paliouras, 2018, 2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST).

Static Delay Variation Models for Ripple-Carry and Borrow-Save Adders

Vassilis Paliouras, Kleanthis Papachatzopoulos, Vassilis Paliouras, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Multirate Fully Parallel LDPC Encoder for the IEEE 802.11n/ac/ax QC-LDPC Codes Based on Reduced Complexity XOR Trees

Vassilis Paliouras, Ahmed Mahdi, N. Kanistras, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Approximate Sorting Check Node Processing in Non-Binary LDPC Decoders

Vassilis Paliouras, Dimitris Chytas, Vassilis Paliouras, 2020, 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

An approximate hardware check node for λ-min-based LDPC decoders

Vassilis Paliouras, Georgios Perris-Samios, Vassilis Paliouras, 2017, 2017 25th European Signal Processing Conference (EUSIPCO).

Novel multi-Gbps bit-flipping decoders for punctured LDPC codes

Vassilis Paliouras, Christina Archonta, Nikos Kanistras, 2016, 2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST).

Approximate Algorithms for Identifying Minima on Min-Sum LDPC Decoders and Their Hardware Implementation

Vassilis Paliouras, I. Tsatsaragkos, Vassilis Paliouras, 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

A semi-analytical bivariate Gaussian model of the approximation error impact on the Min-Sum LDPC decoding algorithm

Vassilis Paliouras, Nikos Kanistras, Vassilis Paliouras, 2013, SiPS 2013 Proceedings.

Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs

Vassilis Paliouras, Ahmed Mahdi, Nikos Kanistras, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

Simplified Multi-Level Quasi-Cyclic LDPC Codes for Low-Complexity Encoders

Vassilis Paliouras, Ahmed Mahdi, Vassilis Paliouras, 2012, 2012 IEEE Workshop on Signal Processing Systems.

Propagation of LLR Saturation and Quantization Error in LDPC Min-Sum Iterative Decoding

Vassilis Paliouras, Nikos Kanistras, I. Tsatsaragkos, 2012, 2012 IEEE Workshop on Signal Processing Systems.

Digital baseband challenges for a 60GHz gigabit link

Vassilis Paliouras, Konstantina Karagianni, Ahmed Mahdi, 2011, 2011 18th IEEE International Conference on Electronics, Circuits, and Systems.

An encoding scheme and encoder architecture for rate-compatible QC-LDPC codes

Vassilis Paliouras, Ahmed Mahdi, Nikos Kanistras, 2011, 2011 IEEE Workshop on Signal Processing Systems (SiPS).

A flexible layered LDPC decoder

Vassilis Paliouras, I. Tsatsaragkos, Vassilis Paliouras, 2011, 2011 8th International Symposium on Wireless Communication Systems.

Multiple LDPC decoder of very low bit-error rate

N. Kanistras, V. Paliouras, I. Tsatsaragkos, 2011, 2011 17th International Conference on Digital Signal Processing (DSP).

A syndrome-based LDPC decoder with very low error floor

N. Kanistras, V. Paliouras, I. Tsatsaragkos, 2011, 2011 17th International Conference on Digital Signal Processing (DSP).

Impact of Approximation Error on the Decisions of LDPC Decoding

Vassilis Paliouras, Nikos Kanistras, Vassilis Paliouras, 2011, J. Signal Process. Syst..

Impact of LLR saturation and quantization on LDPC min-sum decoders

N. Kanistras, V. Paliouras, I. Tsatsaragkos, 2010, 2010 IEEE Workshop On Signal Processing Systems.

Impact of roundoff error on the decisions of the Log Sum-Product algorithm for LDPC decoding

Vassilis Paliouras, N. Kanistras, 2008, 2008 IEEE Workshop on Signal Processing Systems.

On the implementation of bus-based architectures for LDPC decoding

Vassilis Paliouras, G. Aggouras, Vassilis Paliouras, 2008, 2008 3rd International Symposium on Wireless Pervasive Computing.

Impact of roundoff errors in LDPC decoding

Vassilis Paliouras, Nikos Kanistras, Vassilis Paliouras, 2008, 2008 3rd International Symposium on Wireless Pervasive Computing.

An FPGA Accelerator for Spiking Neural Network Simulation and Training

Vassilis Paliouras, Vasilis Sakellariou, Vassilis Paliouras, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

Hardware Implementation of a Softmax-Like Function for Deep Learning

Vassilis Paliouras, Ioannis Kouretas, Vassilis Paliouras, 2020, Technologies.

High-Level Synthesis design approach for Number-Theoretic Transform Implementations

Vassilis Paliouras, A. Fournaris, E. Haleplidis, 2021, IEEE/IFIP International Conference on Very Large Scale Integration of System-on-Chip.

On Reducing the Number of Multiplications in RNS-based CNN Accelerators

Vassilis Paliouras, Thanos Stouraitis, Hani Saleh, 2021, 2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS).

Implementing the Residue Logarithmic Number System Using Interpolation and Cotransformation

Vassilis Paliouras, Mark G. Arnold, Ioannis V. Kouretas, 2020, IEEE Transactions on Computers.

A low-complexity combinatorial RNS multiplier

Vassilis Paliouras, Thanos Stouraitis, K. Karagianni, 2001 .

High-Level Synthesis design approach for Number-Theoretic Multiplier

Vassilis Paliouras, A. Fournaris, E. Haleplidis, 2022, 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC).

A very-long instruction word digital signal processor based on the logarithmic number system

Thanos Stouraitis, V. Paliouras, J. Karagiannis, 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

Modified Logarithmic Multiplication Approximation for Machine Learning

T. Stouraitis, Vassilis Paliouras, I. Kouretas, 2023, 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS).

Using the arithmetic representation properties of data to reduce the area and power consumption of FFT circuits for wireless OFDM systems

Vassilis Paliouras, Andreas Brokalakis, Vassilis Paliouras, 2011, 2011 IEEE Workshop on Signal Processing Systems (SiPS).

Towards a Quaternion Complex Logarithmic Number System

Vassilis Paliouras, Mark G. Arnold, John R. Cowles, 2011, 2011 IEEE 20th Symposium on Computer Arithmetic.

Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters

Vassilis Paliouras, Ioannis Kouretas, Charalambos Basetas, 2008, IEEE Transactions on Computers.

A novel algorithm for accurate logarithmic number system subtraction

Vassilis Paliouras, Thanos Stouraitis, T. Stouraitis, 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

A Multiplier-Free RNS-Based CNN Accelerator Exploiting Bit-Level Sparsity

Vassilis Paliouras, I. Kouretas, Vasilis Sakellariou, 2024, IEEE Transactions on Emerging Topics in Computing.

Hardware Implementation Aspects of a Syndrome-based Neural Network Decoder for BCH Codes

E. Kavvousanos, V. Paliouras, Vassilis Paliouras, 2019, 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).