Y. Nagata

Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory

Y. Iwata, A. Nitayama, H. Tanaka, 2007, 2007 IEEE Symposium on VLSI Technology.

Disturbless flash memory due to high boost efficiency on BiCS structure and optimal memory film stack for ultra high density storage device

Y. Fukuzumi, H. Tanaka, M. Kido, 2008, 2008 IEEE International Electron Devices Meeting.

Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory

Y. Iwata, A. Nitayama, H. Tanaka, 2007, 2007 IEEE International Electron Devices Meeting.

Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices

Y. Iwata, Li Zhang, A. Nitayama, 2006, 2009 Symposium on VLSI Technology.

Optimal device structure for Pipe-shaped BiCS Flash memory for ultra high density storage device with excellent performance and reliability

Takashi Maeda, Akihiro Nitayama, Yoshihisa Iwata, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).