A. Nitayama

发表

Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory

Y. Iwata, A. Nitayama, H. Tanaka, 2007, 2007 IEEE Symposium on VLSI Technology.

A fully planarized 0.25 /spl mu/m CMOS technology for 256 Mbit DRAM and beyond

R. Kleinhenz, T. Mii, H. Aochi, 1995, 1995 Symposium on VLSI Technology. Digest of Technical Papers.

Disturbless flash memory due to high boost efficiency on BiCS structure and optimal memory film stack for ultra high density storage device

Y. Fukuzumi, H. Tanaka, M. Kido, 2008, 2008 IEEE International Electron Devices Meeting.

A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs

S. Inoue, F. Masuoka, A. Nitayama, 1989, International Technical Digest on Electron Devices Meeting.

Reduction of switching current distribution in spin transfer magnetic random access memories

A. Nitayama, M. Nakayama, T. Kai, 2008 .

Effect of Interface Buffer Layer on the Reliability of Ultra-Thin MgO Magnetic Tunnel Junctions for Spin Transfer Switching MRAM

A. Nitayama, N. Shimomura, S. Ikegawa, 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

Semiconductor memory and process for its manufacture

Fumio Horiguchi, Akihiro Nitayama, Kazumasa Sunouchi, 1990 .

Properties of Deep Levels in ZnO Varistors and Their Effect on Current-Response Characteristics

H. Sakaki, A. Nitayama, T. Ikoma, 1980 .

Reduction of Bipolar Disturb of Floating-Body Cell (FBC) by Silicide and Thin Silicon Film Formed at Source and Drain Regions

T. Hamamoto, Y. Fukuzumi, A. Nitayama, 2010, IEEE Transactions on Electron Devices.

VIB-1 new hot-carrier-induced degradation phenomena in half-micrometer MOS transistors

T. Hamamoto, A. Nitayama, Y. Oowaki, 1987, IEEE Transactions on Electron Devices.

A 33ns 64Mb DRAM

Shigeyoshi Watanabe, Fumio Horiguchi, Yukihito Oowaki, 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A Floating Body Cell (FBC) fully Compatible with 90nm CMOS Technology Node for Embedded Applications

Atsushi Sakamoto, Akihiro Nitayama, Takashi Ohsawa, 2006, 2006 IEEE International Conference on IC Design and Technology.

A SrRuO3/IrO2 top electrode FeRAM with Cu BEOL process for embedded memory of 130 nm generation and beyond

A. Nitayama, S. Shiratake, D. Takashima, 2006 .

A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's

Fumio Horiguchi, Yukihito Oowaki, Shigeyoshi Watanabe, 1995 .

Impact of surrounding gate transistor (SGT) for ultra-high-density LSI's

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1991 .

Multi-pillar surrounding gate transistor (M-SGT) for compact and high-speed circuits

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1991 .

Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory

Y. Iwata, A. Nitayama, H. Tanaka, 2007, 2007 IEEE International Electron Devices Meeting.

High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1988, Technical Digest., International Electron Devices Meeting.

A Statistical Model for Assessing the Fault Tolerance of Variable Switching Currents for a 1Gb Spin Transfer Torque Magnetoresistive Random Access Memory

Akihiro Nitayama, Hiroaki Yoda, Tatsuya Kishi, 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

Vertical 3D NAND Flash Memory Technology

H. Aochi, A. Nitayama, 2011 .

Ion Beam Etching Technology for High-Density Spin Transfer Torque Magnetic Random Access Memory

Akihiro Nitayama, Hiroaki Yoda, Naoharu Shimomura, 2009 .

Process Integration of Low-Power and High-Speed 16Mb MRAM using Multi-Layer Wiring Technology

S. Miura, Akihiro Nitayama, Hiroaki Yoda, 2006 .

Effect of Self-Heating on Time-Dependent Dielectric Breakdown in Ultrathin MgO Magnetic Tunnel Junctions for Spin Torque Transfer Switching Magnetic Random Access Memory

Makoto Nagamine, Keiji Hosotani, A. Nitayama, 2010 .

Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices

Y. Iwata, Li Zhang, A. Nitayama, 2006, 2009 Symposium on VLSI Technology.

Floating Body RAM Technology and its Scalability to 32nm Node and Beyond

T. Ohsawa, T. Higashi, A. Nitayama, 2006, 2006 International Electron Devices Meeting.

Fully-depleted FBC (floating body cell) with enlarged signal window and excellent logic process compatibility

Akihiro Nitayama, Takashi Ohsawa, K. Inoh, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Optimal device structure for Pipe-shaped BiCS Flash memory for ultra high density storage device with excellent performance and reliability

Takashi Maeda, Akihiro Nitayama, Yoshihisa Iwata, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Future directions for DRAM memory cell technology

A. Nitayama, Y. Kohyama, K. Hieda, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Scaling scenario of floating body cell (FBC) suppressing Vth variation due to random dopant fluctuation

Akihiro Nitayama, Ryo Fukuda, Takashi Ohsawa, 2008, 2008 IEEE International SOI Conference.

A sub-10-ns 16/spl times/16 multiplier using 0.6-/spl mu/m CMOS technology

Yukihito Oowaki, Shigeyoshi Watanabe, Akihiro Nitayama, 1987 .

Bit Cost Scalable (BiCS) technology for future ultra high density storage memories

Akihiro Nitayama, Hideaki Aochi, H. Aochi, 2013, 2013 Symposium on VLSI Technology.

Double LDD concave (DLC) structure for sub-half micron MOSFET

F. Masuoka, A. Nitayama, K. Sunouchi, 1988, Technical Digest., International Electron Devices Meeting.