V. Narayanan

发表

Mary Jane Irwin, M. J. Irwin, Vijay Narayanan, 1999, 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461).

Fundamental aspects of HfO2-based high-k metal gate stack reliability and implications on tinv-scaling

E. Cartier, V. Narayanan, J. Stathis, 2011, 2011 International Electron Devices Meeting.

Temperature-Dependent – Characteristics of a Vertical Tunnel FET

T. Mayer, V. Narayanan, S. Datta, 2010 .

Advanced gate stacks with fully silicided (FUSI) gates and high-/spl kappa/ dielectrics: enhanced performance at reduced gate leakage

H. Nayfeh, M. Ieong, J. Kedzierski, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

Syed Muhammad Zain Zafar, M. Hargrove, C. Ouyang, 2007, 2007 IEEE Symposium on VLSI Technology.

Maximized Benefit of La–Al–O Higher-$k$ Gate Dielectrics by Optimizing the La/Al Atomic Ratio

A. Kellock, V. Narayanan, J. Bruley, 2011, IEEE Electron Device Letters.

Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond

M. Ieong, E. Cartier, V. Narayanan, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

S. Narasimha, M. Hargrove, R. Pal, 2011, 2011 International Electron Devices Meeting.

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

T. Adam, T. Standaert, M. Khare, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

High performance FDSOI CMOS technology with metal gate and high-k

Anna W. Topol, P. Kirsch, K. Guarini, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

X. Chen, M. Khare, D. Tekleab, 2008, 2008 Symposium on VLSI Technology.

Antiphase boundaries in GaP layers grown on (001) Si by chemical beam epitaxy

V. Narayanan, K. Bachmann, S. Mahajan, 2002 .

A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates

C. Cabral, V. Narayanan, S. Zafar, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Interfacial layer optimization of high-k/metal gate stacks for low temperature processing

E. Cartier, V. Narayanan, B. Linder, 2009 .

Bias temperature instability in High-κ/metal gate transistors - Gate stack scaling trends

E. Cartier, V. Narayanan, J. Stathis, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

Origins of threading dislocations in GaN epitaxial layers grown on sapphire by metalorganic chemical vapor deposition

V. Narayanan, S. Mahajan, K. Lorenz, 2001 .

SOFT ERRORS: MODELING AND INTERACTIONS WITH POWER OPTIMIZATIONS

M. J. Irwin, K. Unlu, V. Narayanan, 2005 .

Temperature-Dependent $I$– $V$ Characteristics of a Vertical $\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$

Suman Datta, Theresa Mayer, Vijay Narayanan, 2010, IEEE Electron Device Letters.

A maximum extreme-value distribution model for switching conductance of oxide-RRAM in memory applications

E. Cartier, V. Narayanan, R. Muralidhar, 2020 .

Process optimizations for NBTI/PBTI for future replacement metal gate technologies

Barry P. Linder, T. Ando, M. Wang, 2016, 2016 IEEE International Reliability Physics Symposium (IRPS).

High-κ/Metal Gate Science and Technology

Supratik Guha, Vijay Narayanan, V. Narayanan, 2009 .

Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process

Y. Liu, T. Nigam, S. Uppal, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

High performance and low leakage current InGaAs-on-silicon FinFETs with 20 nm gate length

M. Krishnan, E. Cartier, V. Narayanan, 2017, 2017 Symposium on VLSI Technology.

Device design considerations for ultra-thin SOI MOSFETs

V. Narayanan, M. Steen, R. Jammy, 2003, IEEE International Electron Devices Meeting 2003.

Gallium nitride epitaxy on (0001) sapphire

V. Narayanan, S. Mahajan, S. Mahajan, 2002 .

Switching of ferroelectric polarization in epitaxial BaTiO₃ films on silicon without a conducting bottom electrode.

Catherine Dubourdieu, Sergei V. Kalinin, Sergei V Kalinin, 2013, Nature nanotechnology.

Extendibility of NiPt silicide to the 22-nm node CMOS technology

Anna W. Topol, K. Ohuchi, V. Narayanan, 2008, Extended Abstracts - 2008 8th International Workshop on Junction Technology (IWJT '08).

A programmable ferroelectric single electron transistor

V. Narayanan, S. Datta, Lu Liu, 2013 .

Differentiated Performance and Reliability Enabled by Multi-Work Function Solution in RMG Silicon and SiGe MOSFETs

T. Ando, R. G. Southwick, V. Narayanan, 2018, 2018 IEEE Symposium on VLSI Technology.

Examination of flatband and threshold voltage tuning of HfO2∕TiN field effect transistors by dielectric cap layers

V. Narayanan, B. Linder, M. Copel, 2007 .

Characterization and optimization of charge trapping in high-k dielectrics

T. Ando, R. Krishnan, V. Narayanan, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Interface engineering for enhanced electron mobilities in W/HfO/sub 2/ gate stacks

A. Curioni, V. Narayanan, R. Jammy, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Poly-Si/high-k gate stacks with near-ideal threshold voltage and mobility

P. Oldiges, K. Maitra, V. Narayanan, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

Interaction of La2O3 capping layers with HfO2 gate dielectrics

Eduard A. Cartier, Supratik Guha, Vijay Narayanan, 2009 .

Origins of Effective Work Function Roll-Off Behavior for High-κ Last Replacement Metal Gate Stacks

E. Cartier, V. Narayanan, J. Bruley, 2013, IEEE Electron Device Letters.

The Interaction Challenges with Novel Materials in Developing High‐Performance and Low‐Leakage High‐k/Metal Gate CMOS Transistors

M. Khare, E. Cartier, V. Narayanan, 2012 .

Epitaxial silicon and germanium on buried insulator heterostructures and devices

Frances M. Ross, Supratik Guha, Vijay Narayanan, 2003 .

Lattice-matched, epitaxial, silicon-insulating lanthanum yttrium oxide heterostructures

V. Narayanan, N. Bojarczuk, S. Guha, 2002 .

High-K Gate Dielectric Structures by Atomic Layer Deposition for the 32nm and Beyond Nodes

V. Narayanan, J. Bruley, H. Jagannathan, 2008 .

Role of point defects and HfO2/TiN interface stoichiometry on effective work function modulation in ultra-scaled complementary metal–oxide–semiconductor devices

V. Narayanan, K. Murali, R. Pandey, 2013 .

High Performance InGaAs Gate-All-Around Nanosheet FET on Si Using Template Assisted Selective Epitaxy

G. Cohen, C. Lavoie, V. Narayanan, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Structural, optical, and electrical properties of strained La-doped SrTiO3 films

Alexander A. Demkov, Martin M. Frank, Stefan Zollner, 2014 .

(Invited) The Past, Present and Future of High-k/Metal Gates

E. Cartier, V. Narayanan, A. Kerber, 2013 .

Potential imaging of Si∕HfO2/polycrystalline silicon gate stacks: Evidence for an oxide dipole

E. Cartier, V. Narayanan, E. Gusev, 2005 .

Metal-oxide based, CMOS-compatible ECRAM for Deep Learning Accelerator

Douglas M. Bishop, P. Solomon, V. Narayanan, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

High-k/Metal Gates- from research to reality

V. Narayanan, 2007, 2007 International Workshop on Physics of Semiconductor Devices.

Two‐Step Epitaxy of Gallium Nitride on (0001) Sapphire

V. Narayanan, S. Mahajan, 2013 .

The physical properties of cubic plasma-enhanced atomic layer deposition TaN films

C. Lavoie, V. Narayanan, Ho-Cheol Kim, 2004 .

Ruthenium based metals using atomic vapor deposition for gate electrode applications

V. Narayanan, T. Ando, C. Choi, 2011 .

HERMES Core – A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing

I. Ahsan, E. Eleftheriou, V. Narayanan, 2021, 2021 Symposium on VLSI Circuits.

Neural network learning using non-ideal resistive memory devices

V. Narayanan, T. Ando, H. Miyazoe, 2022, Frontiers in Nanotechnology.

Fully on-chip MAC at 14nm enabled by accurate row-wise programming of PCM-based weights and parallel vector-transport in duration-format

P. Narayanan, I. Ahsan, G. Burr, 2021, 2021 Symposium on VLSI Technology.

Epitaxial strontium oxide layers on silicon for gate-first and gate-last TiN/HfO2 gate stack scaling

Martin M. Frank, Chiara Marchiori, Jean Fompeyrine, 2011 .

Epitaxial SrO interfacial layers for HfO2–Si gate stack scaling

V. Narayanan, J. Bruley, M. Frank, 2011 .

Replacement metal gate resistance in FinFET architecture modelling, validation and extendibility

S. Grunow, V. Narayanan, J. Bruley, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Understanding and mitigating High-k induced device width and length dependencies for FinFET replacement metal gate technology

V. Narayanan, T. Ando, A. Madan, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh

P. Narayanan, G. Burr, Stanisław Woźniak, 2023, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Influence of AlN nucleation layer growth conditions on quality of GaN layers deposited on (0001) sapphire

V. Narayanan, S. Mahajan, Wook Kim, 2002 .

Interfacial oxide formation and oxygen diffusion in rare earth oxide–silicon epitaxial heterostructures

V. Narayanan, P. Flaitz, M. Copel, 2002 .

Ultra-scaled Conformal Scavenging Electrode with Superior Tunability for Short-channel RMG FinFET Workfunction and all-ALD 3D-compatible ReRAM

E. Cartier, V. Narayanan, J. Bruley, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Simple Gate Metal Anneal (SIGMA) stack for FinFET Replacement Metal Gate toward 14nm and beyond

T. Ando, V. Narayanan, J. Bruley, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

IBM Research Report The Physical Properties of Cubic PE-ALD TaN Films as Ultra-Thin Cu Diffusion Barrier

C. Lavoie, V. Narayanan, Ho-Cheol Kim, 2003 .

Transistor scaling with novel materials

Anna W. Topol, Meikei Ieong, Vijay Narayanan, 2006 .

Erratum: Switching of ferroelectric polarization in epitaxial BaTiO 3 films on silicon without a conducting bottom electrode (Nature Nanotechnology (2013) 8 (748-754))

David J. Frank, Catherine Dubourdieu, Alexander A. Demkov, 2013 .

Signal and noise extraction from analog memory elements for neuromorphic computing

V. Narayanan, A. Sebastian, T. Ando, 2018, Nature Communications.

Resistive Memory Process Optimization for High Resistance Switching Toward Scalable Analog Compute Technology for Deep Learning

M. Rasch, W. Haensch, V. Narayanan, 2021, IEEE Electron Device Letters.

Reliability Challenges with Materials for Analog Computing

Geoffrey W. Burr, Paul M. Solomon, Tayfun Gokmen, 2019, 2019 IEEE International Reliability Physics Symposium (IRPS).

Quasi-damascene metal gate/high-k CMOS using oxygenation through gate electrodes

Martin M. Frank, Eduard A. Cartier, Takashi Ando, 2009 .

Advanced high-k dielectric stacks with polySi and metal gates: Recent progress and current challenges

Martin M. Frank, Vijay Narayanan, Evgeni P. Gusev, 2006, IBM J. Res. Dev..

Fundamental understanding and optimization of PBTI in nFETs with SiO2/HfO2 gate stack

V. Narayanan, E. Cartier, V. Narayanan, 2006, 2006 International Electron Devices Meeting.

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

D. Liu, P. Oldiges, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

Incorporation of la in epitaxial SrTiO3 thin films grown by atomic layer deposition on SrTiO3-buffered Si (001) substrates

Alexander A. Demkov, John G. Ekerdt, Martin M. Frank, 2014 .

Characterization of silicate/Si(001) interfaces

E. Cartier, V. Narayanan, M. Reuter, 2002 .

Oxygen vacancies in high dielectric constant oxide-semiconductor films.

V. Narayanan, S. Guha, 2007, Physical review letters.

Extendibility of NiPt Silicide Contacts for CMOS Technology Demonstrated to the 22-nm Node

Anna W. Topol, M. Khare, C. Lavoie, 2007, 2007 IEEE International Electron Devices Meeting.

Dual workfunction fully silicided metal gates

J. Kedzierski, R. Carruthers, C. Cabral, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Toward High Performance SiGe Channel CMOS: Design of High Electron Mobility in SiGe nFinFETs Outperforming Si

V. Narayanan, H. Jagannathan, P. Hashemi, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

High Mobility High-Ge-Content SiGe PMOSFETs Using Al2O3/HfO2 Stacks With In-Situ O3 Treatment

Kevin K. H. Chan, E. Cartier, V. Narayanan, 2017, IEEE Electron Device Letters.

Comparative study of GaN and AlN nucleation layers and their role in growth of GaN on sapphire by metalorganic chemical vapor deposition

Vijay Narayanan, V. Narayanan, S. Mahajan, 2000 .

Keynote) Challenges of 10 Nm and 7 Nm CMOS for Server and Mobile Applications

Rama Divakaruni, Vijay Narayanan, V. Narayanan, 2016 .

Full metal gate with borderless contact for 14 nm and beyond

B. Haran, V. Narayanan, J. Bruley, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Tunable electrical properties of TaNx thin films grown by ionized physical vapor deposition

A. Kellock, V. Narayanan, M. Frank, 2014 .

The Quantum Metal Ferroelectric Field-Effect Transistor

David J. Frank, Paul M. Solomon, Catherine Dubourdieu, 2014, IEEE Transactions on Electron Devices.

Growth and characterization of epitaxial Si/(LaxY1−x)2O3/Si heterostructures

V. Narayanan, F. Ross, N. Bojarczuk, 2003 .

Influence of Lead Substitution in Zinc Oxide Thin Films

V. Narayanan, K. Ramamurthi, A. Stephen, 2013 .

Interfacial microstructure of NiSix/HfO2/SiOx/Si gate stacks

C. Cabral, V. Narayanan, E. Gusev, 2007 .

Growth of gallium phosphide layers by chemical beam epitaxy on oxide patterned (001)silicon substrates

V. Narayanan, S. Shingubara, K. Bachmann, 1998 .

Impact of metal gates on remote phonon scattering in titanium nitride/hafnium dioxide n-channel metal–oxide–semiconductor field effect transistors–low temperature electron mobility study

Veena Misra, Martin M. Frank, Eduard A. Cartier, 2007 .

Nanotechnology-inspired Information Processing Systems of the Future pdf

Klara Nahrstedt, H.-S. Philip Wong, Naresh Shanbhag, 2020, ArXiv.

Evolution of interfacial Fermi level in In0.53Ga0.47As/high-κ/TiN gate stacks

E. Cartier, V. Narayanan, T. Ando, 2015 .

BEOL Compatible High-Capacitance MIMCAP Structure Using a Novel High k Material

E. Cartier, V. Narayanan, H. Jagannathan, 2020, ECS Meeting Abstracts.

Oxygen migration in TiO2-based higher-k gate stacks

V. Narayanan, J. Bruley, M. Frank, 2010 .

Effect of plasma N2 and thermal NH3 nitridation in HfO2 for ultrathin equivalent oxide thickness

J. Shepard, V. Narayanan, S. Krishnan, 2013 .

High-k Oxides on Si: MOSFET Gate Dielectrics

V. Narayanan, T. Ando, M. Frank, 2016 .

Mechanism and control of the metal-to-insulator transition in rocksalt tantalum nitride

Nathan Newman, V. Narayanan, John M. Rowell, 2002 .

CMOS compatible MIM decoupling capacitor with reliable sub-nm EOT high-k stacks for the 7 nm node and beyond

T. Ando, V. Narayanan, J. Bruley, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

G. Northrop, V. Sardesai, S. Narasimha, 2014, 2014 IEEE International Electron Devices Meeting.

Process and Electrical Characteristics of MO-ALD HfO2 Films for High-k Gate Applications Grown in a Production Worthy 300 mm Deposition System

V. Narayanan, B. Linder, J. Faltermeier, 2007 .

New layout dependency in high-k/Metal Gate MOSFETs

M. Sherony, F. Arnaud, F. Matsuoka, 2011, 2011 International Electron Devices Meeting.

Mushroom-Type phase change memory with projection liner: An array-level demonstration of conductance drift and noise mitigation

S. Ambrogio, A. Sebastian, T. Yamashita, 2021, 2021 IEEE International Reliability Physics Symposium (IRPS).

Scaling the MOSFET gate dielectric: From high-k to higher-k? (Invited Paper)

Martin M. Frank, Michael P. Chudzik, Vijay Narayanan, 2009 .

Charge Defects, Vt Shifts, and the Solution to the High-K Metal Gate n-MOSFET Problem

V. Narayanan, B. Linder, M. Copel, 2006 .

High performance and reliable strained SiGe PMOS FinFETs enabled by advanced gate stack engineering

Eduard A. Cartier, Takashi Ando, Vijay Narayanan, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

High performance and record subthreshold swing demonstration in scaled RMG SiGe FinFETs with high-Ge-content channels formed by 3D condensation and a novel gate stack process

T. Ando, V. Narayanan, E. Leobandung, 2017, 2017 Symposium on VLSI Technology.

PBTI in InGaAs MOS capacitors with Al2O3/HfO2/TiN gate stacks: Interface-state generation

Martin M. Frank, Takashi Ando, Vijay Narayanan, 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

A comparative study of strain and Ge content in Si1−xGex channel using planar FETs, FinFETs, and strained relaxed buffer layer FinFETs

B. Haran, V. Narayanan, H. Jagannathan, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Critical Elements for Next Generation High Performance Computing Nanosheet Technology

V. Narayanan, D. Guo, E. Leobandung, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

High performance PMOS with strained high-Ge-content SiGe fins for advanced logic applications

Kevin K. H. Chan, V. Narayanan, J. Bruley, 2017, 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Replacement high-K/metal-gate High-Ge-content strained SiGe FinFETs with high hole mobility and excellent SS and reliability at aggressive EOT ∼7Å and scaled dimensions down to sub-4nm fin widths

T. Ando, V. Narayanan, E. Leobandung, 2016, 2016 IEEE Symposium on VLSI Technology.

Recent advances and current challenges in the search for high mobility band-edge high-k/metal gate stacks

E. Cartier, V. Narayanan, B. Linder, 2007 .

Epitaxial Si films Grown on Lattice Matched (La x Y 1-x )O 3 /Si (111) Structures by Molecular Beam Epitaxy

V. Narayanan, M. Copel, N. Bojarczuk, 2002 .

High-$\kappa$/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length

W. Haensch, C. Lavoie, V. Narayanan, 2010, IEEE Electron Device Letters.

Dual layer SrTiO3/HfO2 gate dielectric for aggressively scaled band-edge nMOS devices

M. Khare, E. Cartier, V. Narayanan, 2007 .

(Invited) Ultimate EOT Scaling (< 5Aå) Using Hf-Based High-κ Gate Dielectrics and Impact on Carrier Mobility

V. Narayanan, J. Bruley, H. Arimura, 2010 .

Materials and Process Integration Issues in Metal Gate/High-k Stacks and Their Dependence on Device Performance

V. Narayanan, S. Zafar, K. Babich, 2007 .

Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT

Jie Yang, Terence B. Hook, Andreas Knorr, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

High temperature (1000 °C) compatible Y―La―Si―O silicate gate dielectric in direct contact with Si with 7.7 A equivalent oxide thickness

E. Cartier, V. Narayanan, J. Bruley, 2011 .

Physical origins of mobility degradation in extremely scaled SiO2/HfO2 gate stacks with La and Al induced dipoles

V. Narayanan, J. Bruley, T. Ando, 2010 .

Temperature-dependent La- and Al-induced dipole behavior monitored by femtosecond pump/probe photoelectron spectroscopy

Takashi Ando, Alessandro C. Callegari, Andrew J. Kellock, 2010 .

Understanding mobility mechanisms in extremely scaled HfO2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and Vt-tuning dipoles with gate-first process

T. Ando, V. Narayanan, A. Kerber, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Engineering High Dielectric Constant Materials for Band-Edge CMOS Applications

Hemanth Jagannathan, Vijay Narayanan, V. Narayanan, 2008 .

Process optimization for high electron mobility in nMOSFETs with aggressively scaled HfO/sub 2//metal stacks

K. Maitra, V. Narayanan, R. Carruthers, 2006, IEEE Electron Device Letters.

Extremely scaled gate-first high-k/metal gate stack with EOT of 0.55 nm using novel interfacial layer scavenging techniques for 22nm technology node and beyond

E. Cartier, V. Narayanan, J. Bruley, 2006, 2009 Symposium on VLSI Technology.

Deep learning acceleration in 14nm CMOS compatible ReRAM array: device, material and algorithm co-optimization

M. Rasch, V. Narayanan, R. Johnson, 2022, 2022 International Electron Devices Meeting (IEDM).

Characterizing the soft error vulnerability of multicores running multithreaded applications

Anand Sivasubramaniam, Niranjan Soundararajan, Vijay Narayanan, 2010, SIGMETRICS '10.

Role of oxygen vacancies in V/sub FB//V/sub t/ stability of pFET metals on HfO/sub 2/

E. Cartier, F.R. McFeely, V. Narayanan, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

NFET effective work function improvement via stress memorization technique in replacement metal gate technology

Y. Liu, S. Jain, S. Samavedam, 2013, 2013 Symposium on VLSI Technology.

Process and local layout effect interaction on a high performance planar 20nm CMOS

S. Samavedam, M. Sherony, X. Wu, 2013, 2013 Symposium on VLSI Technology.

Trigate 6T SRAM scaling to 0.06 µm2

E. Joseph, W. Haensch, Y. Zhang, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).