R. Johnson

发表

A 0.18 /spl mu/m BiCMOS technology featuring 120/100 GHz (f/sub T//f/sub max/) HBT and ASIC-compatible CMOS using copper interconnect

B. Jagannathan, R. Groves, J. Johnson, 2001, Proceedings of the 2001 BIPOLAR/BiCMOS Circuits and Technology Meeting (Cat. No.01CH37212).

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

L. H. Vanamurth, D. Yang, T. Adam, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

T. Adam, T. Standaert, M. Khare, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

H. Sunamura, T. Yamamoto, B. Haran, 2010, 2010 Symposium on VLSI Technology.

Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain

T. Adam, J. Holt, B. Haran, 2006, 2009 Symposium on VLSI Technology.

Emitter base junction ESD reliability of an epitaxial base silicon germanium heterojunction bipolar transistor

L. Lanzerotti, R. Johnson, S. Voldman, 2001, Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548).

Electrostatic discharge and high current pulse characterization of epitaxial-base silicon-germanium heterojunction bipolar transistors

A. Joseph, D. Harame, R. Johnson, 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).

Electrostatic discharge characterization of epitaxial-base silicon-germanium heterojunction bipolar transistors

A. Joseph, D. Harame, L. Lanzerotti, 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

Current status and future trends of SiGe BiCMOS technology

Alvin J. Joseph, James S. Dunn, David L. Harame, 2001 .

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

K. Maitra, P. Kulkarni, T. Yamashita, 2010, 2010 Symposium on VLSI Technology.

High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond

M. Khare, S. Luning, O. Faynot, 2013, 2013 IEEE International Electron Devices Meeting.

COM2 enhanced graded base SiGe technology for high speed applications

P. Smith, R. Johnson, T. Sorsch, 2002, 2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No.02CH37278).

Trends in silicon germanium BiCMOS integration and reliability

D. Ahlgren, G. Freeman, S. Subbanna, 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).

First Experimental Demonstration of MRAM Data Scrubbing: 80 Mb MRAM with 40 nm junctions for Last Level Cache Applications

D. Edelstein, R. Johnson, J. Slaughter, 2021, International Electron Devices Meeting.

A 14 nm Embedded STT-MRAM CMOS Technology

T. Standaert, D. Edelstein, R. Johnson, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

O. Faynot, Y. Escarabajal, B. Lherron, 2014, 2014 IEEE International Electron Devices Meeting.

UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below

O. Rozeau, O. Faynot, M. Vinet, 2012, 2012 International Electron Devices Meeting.

High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET

M. Vinet, L. Grenouillet, T. Nagumo, 2012, 2012 International Electron Devices Meeting.

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

B. Jagannathan, N. Loubet, P. Kulkarni, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Wafer-scale oxide fusion bonding and wafer thinning development for 3D systems integration: Oxide fusion wafer bonding and wafer thinning development for TSV-last integration

R. Hannon, S. Kanakasabapathy, A. Upham, 2012, 2012 3rd IEEE International Workshop on Low Temperature Bonding for 3D Integration.

Sub-25nm FinFET with advanced fin formation and short channel effect engineering

K. Maitra, P. Kulkarni, T. Yamashita, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Deep learning acceleration in 14nm CMOS compatible ReRAM array: device, material and algorithm co-optimization

M. Rasch, V. Narayanan, R. Johnson, 2022, 2022 International Electron Devices Meeting (IEDM).