C. Tsang

发表

3D copper TSV integration, testing and reliability

W. Landers, R. Volant, M. Farooq, 2011, 2011 International Electron Devices Meeting.

System-on-package (SOP) technology, characterization and applications

P. Andry, C. Tsang, E. Sprogis, 2006, 56th Electronic Components and Technology Conference 2006.

3D silicon integration

B. Dang, P. Andry, C. Tsang, 2008, 2008 58th Electronic Components and Technology Conference.

An 8×10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects

S. Rylov, X. Gu, B. Dang, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

Characterization of flip chip microjoins up to 40 GHz using silicon carrier

K. Jenkins, B. Dang, P. Andry, 2005, Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..

3D chip stack with integrated decoupling capacitors

B. Dang, P. Andry, C. Tsang, 2009, 2009 59th Electronic Components and Technology Conference.

Terabus: Terabit/Second-Class Card-Level Optical Interconnect Technologies

L. Schares, C. Schow, R. John, 2006, IEEE Journal of Selected Topics in Quantum Electronics.

Terabit/s-Class Optical PCB Links Incorporating 360-Gb/s Bidirectional 850 nm Parallel Optical Transceivers

C. Schow, C. Tsang, J. Knickerbocker, 2012, Journal of Lightwave Technology.

Silicon Carrier with Deep Through-Vias, Fine Pitch Wiring and Through Cavity for Parallel Optical Transceiver

D. Edelstein, P. Andry, C. Tsang, 2005, Proceedings Electronic Components and Technology, 2005. ECTC '05..

CMOS-Compatible Through Silicon Vias for 3D Process Integration

P. Andry, C. Tsang, E. Sprogis, 2006 .

High-density silicon carrier transmission line design for chip-to-chip interconnects

X. Gu, B. Dang, P. Andry, 2011, 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems.

Characterization of micro-bump C4 interconnects for Si-carrier SOP applications

P. Andry, C. Tsang, E. Sprogis, 2006, 56th Electronic Components and Technology Conference 2006.

3D Chip stacking with 50 μm pitch lead-free micro-c4 interconnections

B. Dang, P. Andry, C. Tsang, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

Terabit/s-class 24-channel bidirectional optical transceiver module based on TSV Si carrier for board-level interconnects

Benjamin G. Lee, C. Schow, R. John, 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

300-Gb/s 24-channel bidirectional Si carrier transceiver Optochip for board-level interconnects

C. Schow, C. Tsang, J. Knickerbocker, 2008, 2008 58th Electronic Components and Technology Conference.

IMC bonding for 3D interconnection

H. Noma, P. Andry, C. Tsang, 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

A CMOS-compatible process for fabricating electrical through-vias in silicon

J. Knickerbocker, E. Sprogis, P. Andry, 2006, 56th Electronic Components and Technology Conference 2006.

Pb-free microjoints (50 /spl mu/m pitch) for the next generation microsystems: the fabrication, assembly and characterization

J. Knickerbocker, E. Sprogis, K. Lee, 2006, 56th Electronic Components and Technology Conference 2006.

3D Chip Stacking Technology with Low-Volume Lead-Free Interconnections

B. Dang, Sung K. Kang, B. Webb, 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

Micro-interconnection reliability: Thermal, electrical and mechanical stress

S. L. Wright, B. Dang, J. Knickerbocker, 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

Assembly, Characterization, and Reworkability of Pb-free Ultra-Fine Pitch C4s for System-on-Package

A. Sharma, B. Dang, K. Sakuma, 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

Assembly and packaging of non-bumped 3D chip stacks on bumped substrates

B. Dang, P. Andry, C. Tsang, 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

50μm pitch Pb-free micro-bumps by C4NP technology

Bing Dang, Da-Yuan Shih, K. Ruhmer, 2008, 2008 58th Electronic Components and Technology Conference.

Integration and Packaging of Embedded Radial Micro-Channels for 3D Chip Cooling

M. Schultz, B. Dang, C. Tsang, 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

Local Measurements of Flow Boiling Heat Transfer on Hot Spots in 3D Compatible Radial Microchannels

M. Schultz, B. Dang, C. Tsang, 2015 .

Advanced wafer bonding and laser debonding

B. Dang, P. Andry, C. Tsang, 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

Watson Women's Network Leadership: A Best Practice at IBM Research for Innovative and Effective Recruitment and Retention

Anna W. Topol, J. Snowdon, E. Duesterwald, 2008 .

3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections

Katsuyuki Sakuma, Paul S. Andry, Cornelia K. Tsang, 2008, IBM J. Res. Dev..

Chip-to-chip optical interconnects

P. Chiniwalla, J. Rosner, D. Kucharski, 2006, 2006 Optical Fiber Communication Conference and the National Fiber Optic Engineers Conference.

CMOS compatible thin wafer processing using temporary mechanical wafer, adhesive and laser release of thin chips/wafers for 3D integration

Bing Dang, Robert Trzcinski, John Knickerbocker, 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

Three-dimensional silicon integration

Katsuyuki Sakuma, Anna W. Topol, Paul S. Andry, 2008, IBM J. Res. Dev..

Structure, Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits

Anna W. Topol, Jian-Qiang Lu, Kuan-Neng Chen, 2006, 2006 International Electron Devices Meeting.

High-efficiency 60 GHZ antenna fabricated using low-cost silicon micromachining techniques

B. Gaucher, U. Pfeiffer, J. Grzyb, 2007, 2007 IEEE Antennas and Propagation Society International Symposium.

3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias

S.L. Wright, Hua Gan, C.S. Patel, 2006, IEEE Journal of Solid-State Circuits.

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

Keith A. Jenkins, Alina Deutsch, Paul S. Andry, 2005, IBM J. Res. Dev..

Three-Dimensional Chip Stack With Integrated Decoupling Capacitors and Thru-Si Via Interconnects

Bing Dang, M Shapiro, P Andry, 2010, IEEE Electron Device Letters.

Fabrication and characterization of robust through-silicon vias for silicon-carrier applications

Paul S. Andry, Cornelia K. Tsang, Bucknell C. Webb, 2008, IBM J. Res. Dev..

3D chip stacking with C4 technology

Katsuyuki Sakuma, Paul S. Andry, Cornelia K. Tsang, 2008, IBM J. Res. Dev..

Factors in the selection of temporary wafer handlers for 3D/2.5D integration

Bing Dang, John Knickerbocker, Paul Andry, 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).