J. Safran

3D copper TSV integration, testing and reliability

W. Landers, R. Volant, M. Farooq, 2011, 2011 International Electron Devices Meeting.

3D stackable 32nm High-K/Metal Gate SOI embedded DRAM prototype

C. Kothandaraman, B. Himmel, J. Safran, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

Amplifier in a 0.12µm SOI CMOS

Jean-Olivier Plouchart, Jonghae Kim, Robert A. Groves, 2004 .

Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips

Xiang Chen, Subramanian S. Iyer, Toshiaki Kirihata, 2007, 2007 IEEE Custom Integrated Circuits Conference.

A high-density logic-on-logic 3DIC design using face-to-face hybrid wafer-bonding on 12nm FinFET process

B. Cline, J. Safran, D. Berger, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS

Brian Reed, Subramanian S. Iyer, Toshiaki Kirihata, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Reliability Investigation of NiPtSi Electrical Fuse With Different Programming Mechanisms

C. Tian, C. Kothandaraman, J. Safran, 2007, IEEE Transactions on Device and Materials Reliability.

Reliability Qualification of CoSi2 Electrical Fuse for 90Nm Technology

S.S. Iyer, J. Safran, N. Robson, 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.