Sharad Sinha

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Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System pdf

Wei Zhang, Sharad Sinha, Zhe Lin, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Survey of Algorithmic and Hardware Optimization Techniques for Vision Convolutional Neural Networks on FPGAs

Sharad Sinha, Arish Sateesan, Smitha K. G., 2021, Neural Processing Letters.

Modeling Architecture Extraction Activity Acquisition Feature Construction Power Inference Power Estimator Architecture Extraction Activity Acquisition Feature Construction

Zhe Lin, Sharad Sinha, Wei Zhang, 2022 .

HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis

Jieru Zhao, Sharad Sinha, Wei Zhang, 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications

Yun Liang, Bingsheng He, Sharad Sinha, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA

Bingsheng He, Liang Feng, Wei Zhang, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications

S. Shen, Sharad Sinha, Wei Zhang, 2020, 2020 30th International Conference on Field-Programmable Logic and Applications (FPL).

A Survey of Algorithmic and Hardware Optimization Techniques for Vision Convolutional Neural Networks on FPGAs

Kavallur Gopi Smitha, Sharad Sinha, A. P. Vinod, 2021, Neural Process. Lett..

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis

Jieru Zhao, Sharad Sinha, Tingyuan Liang, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms

Wei Zhang, Hao Liang, Sharad Sinha, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Workload Characterization in HPC Environment for Auto-scaling of Resources – Preliminary Study

Sharad Sinha, R. Hardikar, Mahesh Barve, 2022, IEEE India Conference.

Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective

Thambipillai Srikanthan, Sharad Sinha, T. Srikanthan, 2014, TODE.

Extended Compatibility Path Based Hardware binding: an Adaptive Algorithm for High Level synthesis of Area-Time Efficient Designs

Thambipillai Srikanthan, Udit Dhawan, Sharad Sinha, 2014, J. Circuits Syst. Comput..

A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis

Thambipillai Srikanthan, Siew Kei Lam, Udit Dhawan, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

Intelligent high level synthesis for customization on reconfigurable platforms

Sharad Sinha, Sharad Sinha, 2014 .

Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic Transform

Sarveswara Reddy Sathi, W. Zhang, Sharad Sinha, 2023, 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

FinTech: The New Frontier

Sharad Sinha, Sharad Sinha, 2017, IEEE Potentials.

Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis

Wei Zhang, Liang Feng, Jieru Zhao, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA

Wei Zhang, Zhe Lin, Sharad Sinha, 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling

Sharad Sinha, Wei Zhang, Hao Liang, 2020, ACM Trans. Reconfigurable Technol. Syst..

Static hardware task placement on multi-context FPGA using hybrid genetic algorithm

Wei Zhang, Hao Liang, Sharad Sinha, 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power

Sharad Sinha, Zhe Lin, Wei Zhang, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA

W. Zhang, Sharad Sinha, Gengjie Chen, 2022, ArXiv.

Extended compatibility path based hardware binding algorithm for area-time efficient designs

Thambipillai Srikanthan, Udit Dhawan, Sharad Sinha, 2010, 2nd Asia Symposium on Quality Electronic Design (ASQED).

HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS

W. Zhang, Zhe Lin, Sharad Sinha, 2023, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs

Sharad Sinha, Tingyuan Liang, Linfeng Du, 2024, ACM Transactions on Reconfigurable Technology and Systems.