A. Veidenbaum

Alexander V. Veidenbaum, Sunil Kim, A. Veidenbaum, 1997, Proceedings 1997 International Conference on Parallel Architectures and Compilation Techniques.

Design and Analysis of a Scalable, Shared-memory System with Support for Burst Traffic *

Alexander V. Veidenbaum, Elana D. Granston, Stephen W. Turner, 1992 .

Performance of a shared memory system for vector multiprocessors

Alexander V. Veidenbaum, Stephen W. Turner, A. Veidenbaum, 1988, ICS '88.

OpenCV.js: computer vision processing for the open web platform

Alexander V. Veidenbaum, Alexandru Nicolau, Mohammad R. Haghighat, 2018, MMSys.

WebRTCbench: a benchmark for performance assessment of webRTC implementations

Alexander V. Veidenbaum, Alexandru Nicolau, Qiang Lu, 2015, 2015 13th IEEE Symposium on Embedded Systems For Real-time Multimedia (ESTIMedia).

Compiler-directed cache management in multiprocessors

Alexander V. Veidenbaum, Hoichi Cheong, A. Veidenbaum, 1990, Computer.

A Compiler-Assisted Cache Coherence Solution for Multiprcessors

Alexander V. Veidenbaum, A. Veidenbaum, 1986, ICPP.

Improving Cache Management Policies Using Dynamic Reuse Distances

Mateo Valero, Alexander V. Veidenbaum, Rosario Cammarota, 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

DotHash: Estimating Set Similarity Metrics for Link Prediction and Document Deduplication

T. Givargis, A. Veidenbaum, Mike Heddes, 2023, ArXiv.

High performance annotation-aware JVM for Java cards

Alexander V. Veidenbaum, Alexandru Nicolau, Ana Azevedo, 2005, EMSOFT.

Polygonal Iteration Space Partitioning

Alexander V. Veidenbaum, Alexandru Nicolau, Mario Mango Furnari, 2016, LCPC.

Cache-aware partitioning of multi-dimensional iteration spaces

Alexander V. Veidenbaum, Alexandru Nicolau, Constantine D. Polychronopoulos, 2009, SYSTOR '09.

Interconnection network organization and its impact on performance and cost in shared memory multiprocessors

Alexander V. Veidenbaum, Sunil Kim, A. Veidenbaum, 1999, Parallel Comput..

An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors1

Alexander V. Veidenbaum, Edward H. Gornish, A. Veidenbaum, 1994, 1994 Internatonal Conference on Parallel Processing Vol. 2.

Line size adaptivity analysis of parameterized loop nests for direct mapped data cache

Rajesh K. Gupta, Alexander V. Veidenbaum, Alexandru Nicolau, 2005, IEEE Transactions on Computers.

Understanding and comparing the performance of optimized JVMs

A. Veidenbaum, D. Nicolaescu, A. Veidenbaum, 2005, Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05).

Just in Time Load Balancing

Alexander V. Veidenbaum, Alexandru Nicolau, Rosario Cammarota, 2012, LCPC.

Performance Evaluation of Memory Caches in Multiprocessors

Alexander V. Veidenbaum, Yung-Chin Chen, A. Veidenbaum, 1993, 1993 International Conference on Parallel Processing - ICPP'93.

Dynamic-vector execution on a general purpose EDGE chip multiprocessor

Mateo Valero, Osman S. Unsal, Alexander V. Veidenbaum, 2014, 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV).

Adapting cache line size to application behavior

Rajesh K. Gupta, Weiyu Tang, Alexander V. Veidenbaum, 1999, ICS '99.

Adaptive Line Size Cache

Rajesh Gupta, Weiyu Tang, Alexander V. Veidenbaum, 1999 .

Reducing power consumption for high-associativity data caches in embedded processors

Alexander V. Veidenbaum, Alexandru Nicolau, Dan Nicolaescu, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Proceedings of the 14th international conference on Supercomputing

Alexander V. Veidenbaum, John Reynders, A. Veidenbaum, 2000 .

On leakage power optimization in clock tree networks for ASICs and general-purpose processors

Houman Homayoun, Fadi J. Kurdahi, Alexander V. Veidenbaum, 2011, Sustain. Comput. Informatics Syst..

Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks

Houman Homayoun, Fadi J. Kurdahi, Alexander V. Veidenbaum, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

Beyond memory cells for leakage and temperature control in sram-based units, the peripheral circuits story

Houman Homayoun, Alexander V. Veidenbaum, A. Veidenbaum, 2010 .

An Integrated Hardware/Software Solution for Effective Management of Local Storage in High-Performance Systems

Alexander V. Veidenbaum, Elana D. Granston, A. Veidenbaum, 1991, ICPP.

Performance Characterization of Itanium® 2-Based Montecito Processor

Alexander V. Veidenbaum, Alexandru Nicolau, Arun Kejariwal, 2009, SPEC Benchmark Workshop.

Improving branch prediction accuracy in embedded processors in the presence of context switches

Alexander V. Veidenbaum, Sudeep Pasricha, S. Pasricha, 2003, Proceedings 21st International Conference on Computer Design.

Reducing power with an L0 instruction cache using history-based prediction

Weiyu Tang, Alexander V. Veidenbaum, Alexandru Nicolau, 2002, International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems.

Torchhd: An Open Source Python Library to Support Research on Hyperdimensional Computing and Vector Symbolic Architectures

T. Givargis, A. Veidenbaum, Mike Heddes, 2022, 2205.09208.

Hyperdimensional hashing: a robust and efficient dynamic hash table

T. Givargis, A. Veidenbaum, Igor Nunes, 2022, DAC.

Class-Modeling of Septic Shock With Hyperdimensional Computing

T. Givargis, A. Veidenbaum, Alexandru Nicolau, 2021, 2021 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC).

Detecting COVID-19 Related Pneumonia On CT Scans Using Hyperdimensional Computing

A. Nicolau, T. Givargis, A. Veidenbaum, 2021, 2021 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC).

Using Hardware Counters to Predict Vectorization

Alexander V. Veidenbaum, Alexandru Nicolau, Zhi Chen, 2017, LCPC.

On the Determination of Inlining Vectors for Program Optimization

Alexander V. Veidenbaum, Alexandru Nicolau, Debora Donato, 2013, CC.

Pruning hardware evaluation space via correlation-driven application similarity analysis

Alexander V. Veidenbaum, Alexandru Nicolau, Arun Kejariwal, 2011, CF '11.

A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors

J. Krichmar, A. Nicolau, N. Dutt, 2009, Neural Networks.

On the exploitation of loop-level parallelism in embedded applications

Milind Girkar, Xinmin Tian, Alexander V. Veidenbaum, 2009, TECS.

A Compilation and Run-Time Framework for Maximizing Performance of Self-scheduling Algorithms

Alexander V. Veidenbaum, Alexandru Nicolau, Yizhuo Wang, 2014, NPC.

Improving SDRAM access energy efficiency for low-power embedded systems

Alexander V. Veidenbaum, Arun Kejariwal, Jelena Trajkovic, 2008, TECS.

A distributed processor state management architecture for large-window processors

Mateo Valero, Alexander V. Veidenbaum, Adrián Cristal, 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

On shortest path routing in single stage shuffle-exchange networks

Alexander V. Veidenbaum, Sunil Kim, A. Veidenbaum, 1995, SPAA '95.

NumbaSummarizer: A Python Library for Simplified Vectorization Reports

Alexandru Nicolau, Neftali Watkinson, Alexander Veidenbaum, 2020, 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW).

MCompiler: A Synergistic Compilation Framework pdf

Alexander V. Veidenbaum, Alexandru Nicolau, Aniket Shivam, 2019, ArXiv.

Teaching Parallel Computing and Dependence Analysis with Python

Alexandru Nicolau, Neftali Watkinson, Aniket Shivam, 2019, 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW).

An empirical study of the effect of source-level loop transformations on compiler stability

Zhi Chen, Josep Torrellas, David A. Padua, 2018, Proc. ACM Program. Lang..

Towards an Achievable Performance for the Loop Nests

David A. Padua, Alexander V. Veidenbaum, Alexandru Nicolau, 2018, LCPC.

Using Data Dependence Analysis and Loop Transformations to Teach Vectorization

Alexandru Nicolau, Zhi Chen, Neftali Watkinson, 2017, 2017 International Conference on Computational Science and Computational Intelligence (CSCI).

LORE: A loop repository for the evaluation of compilers

Zhi Chen, Josep Torrellas, David A. Padua, 2017, 2017 IEEE International Symposium on Workload Characterization (IISWC).

Large-scale neural circuit mapping data analysis accelerated with the graphical processing unit (GPU)

Alexander V. Veidenbaum, Xiangmin Xu, Alex Nicolau, 2015, Journal of Neuroscience Methods.

A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors

J. Krichmar, N. Dutt, A. Veidenbaum, 2009, Neural Networks.

Efficient Scheduling of Nested Parallel Loops on Multi-Core Systems

Alexander V. Veidenbaum, Alexandru Nicolau, Constantine D. Polychronopoulos, 2009, 2009 International Conference on Parallel Processing.

Cache-aware iteration space partitioning

Alexander V. Veidenbaum, Alexandru Nicolau, Constantine D. Polychronopoulos, 2008, PPoPP.

Non-Sequential Instruction Cache Prefetching for Multiple-Issue Processors

Alexander V. Veidenbaum, Qingbo Zhao, Abduhl Shameer, 1999, Int. J. High Speed Comput..

Instruction Cache Prefetching Using Multilevel Branch Prediction

Alexander V. Veidenbaum, A. Veidenbaum, 1997, ISHPC.

An effective write policy for software coherence schemes

Alexander V. Veidenbaum, Yung-Chin Chen, A. Veidenbaum, 1992, Proceedings Supercomputing '92.

Author retrospective for compiler-directed data prefetching in multiprocessors with memory hierarchies

Elana D. Granston, Edward H. Gornish, A. Veidenbaum, 2014, ICS 25th Anniversary.

Combining flow and dependence analyses to expose redundant array accesses

Alexander V. Veidenbaum, Elana D. Granston, A. Veidenbaum, 1995, International Journal of Parallel Programming.

Data-rate-aware FPGA-based acceleration framework for streaming applications

Alexander V. Veidenbaum, Alexandru Nicolau, Elaheh Bozorgzadeh, 2016, 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

Increasing the lookahead of multilevel branch prediction

A.V. Veidenbaum, A. Veidenbaum, 1998, Innovative Architecture for Future Generation High-Performance Processors and Systems.

Brain Derived Vision Algorithm on High Performance Architectures

Nikil D. Dutt, Alexander V. Veidenbaum, Alexandru Nicolau, 2009, International Journal of Parallel Programming.

Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems

Houman Homayoun, Kazutoshi Wakabayashi, Alexander V. Veidenbaum, 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

Torchhd: An Open Source Python Library to Support Research on Hyperdimensional Computing and Vector Symbolic Architectures

T. Givargis, A. Veidenbaum, Igor Nunes, 2022, J. Mach. Learn. Res..

Stride-directed prefetching for secondary caches

Alexander V. Veidenbaum, Sunil Kim, A. Veidenbaum, 1997, Proceedings of the 1997 International Conference on Parallel Processing (Cat. No.97TB100162).

SIMD-based soft error detection

Zhi Chen, Alexander V. Veidenbaum, Alexandru Nicolau, 2016, Conf. Computing Frontiers.

Software fault tolerance for FPUs via vectorization

Zhi Chen, Alexander V. Veidenbaum, Alexandru Nicolau, 2015, 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS).

A fault tolerant self-scheduling scheme for parallel loops on shared memory systems

Alexander V. Veidenbaum, Alexandru Nicolau, Yizhuo Wang, 2012, 2012 19th International Conference on High Performance Computing.

Fault Tolerance for FPUs via Vectorization

A. Nicolau, A. Veidenbaum, R. Inagaki, 2015 .