D. Stepanovic

A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS

Borivoje Nikolic, Dusan Stepanovic, B. Nikolić, 2013, IEEE Journal of Solid-State Circuits.

A 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOS

Borivoje Nikolic, Dusan Stepanovic, B. Nikolić, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

Calibration Techniques for Time-Interleaved SAR A/D Converters

Dusan Vlastimir Stepanovic, D. Stepanovic, 2012 .

16.5 An 8GS/s time-interleaved SAR ADC with unresolved decision detection achieving −58dBFS noise and 4GHz bandwidth in 28nm CMOS

Ken Nishimura, Charles Wu, John P. Keane, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).