G. Vandenberghe

发表

Characterization and control of dynamic lens heating effects under high volume manufacturing conditions

S. Hunsche, G. Vandenberghe, P. van Adrichem, 2011, Advanced Lithography.

Freeform illumination sources: an experimental study of source-mask optimization for 22-nm SRAM cells

G. Vandenberghe, J. Finders, S. Verhaegen, 2010, Advanced Lithography.

Printing the metal and contact layers for the 32- and 22-nm node: comparing positive and negative tone development process

Shinji Tarutani, V. Truffert, G. Vandenberghe, 2010, Advanced Lithography.

Calibrated PSCAR stochastic simulation

Geert Vandenberghe, Hans-Jürgen Stock, Peter De Bisschop, 2019, Advanced Lithography.

Characterizing and modeling electrical response to light for metal-based EUV photoresists

Geert Vandenberghe, John J. Biafore, Danilo De Simone, 2016, SPIE Advanced Lithography.

Photoresists in extreme ultraviolet lithography (EUVL)

G. Vandenberghe, D. de Simone, Y. Vesters, 2017 .

Separable OPC models for computational lithography

Lieve Van Look, Geert Vandenberghe, Jo Finders, 2008, Photomask Japan.

Metal Sensitizer in Chemically Amplified EUV Resist: a Study of Sensitivity Enhancement and Dissolution

Geert Vandenberghe, Jing Jiang, Danilo De Simone, 2017 .

PSCAR optimization to reduce EUV resist roughness with sensitization using Resist Formulation Optimizer (RFO)

Geert Vandenberghe, Hans-Jürgen Stock, Peter De Bisschop, 2019, Advanced Lithography.

Constructing a robust PSCAR process for EUV

G. Vandenberghe, K. Nafus, S. Biesemans, 2018, Advanced Lithography.

Litho variations and their impact on the electrical yield of a 32nm node 6TSRAM cell design for manufacturability through design-proces integration II

Geert Vandenberghe, Wim Dehaene, Staf Verhaegen, 2008 .

Integration of tall triple-gate devices with inserted TaxNy gate in a 0.274µm2 6T-SRAM cell and advanced CMOS logic circuits

Vincent Wiaux, Geert Vandenberghe, Patrick Jaenen, 2005 .

Templated DSA vias in sub-7 nm circuits: Design strategy and DSA-aware via decomposition

Geert Vandenberghe, H.-S. Philip Wong, Wim Dehaene, 2016 .

Recent Progress in ArF Lithography for the 100nm Node.

G. Vandenberghe, M. Maenhoudt, I. Pollentier, 2001 .

DSA as a complementary lithography technique for contact hole patterning

B. T. Chan, G. Vandenberghe, R. Gronheid, 2013 .

Metal oxide EUV photoresist performance for N7 relevant patterns and processes

Geert Vandenberghe, Peter De Schepper, Danilo De Simone, 2016, SPIE Advanced Lithography.

AttPSM CD control: mask bias and flare effects

Kurt G. Ronse, Young-Chang Kim, Geert Vandenberghe, 2002, SPIE Advanced Lithography.

Improved resolution with main chain scission resists for EUV lithography

G. Vandenberghe, Ashish Rathore, M. Hoshino, 2022, Advanced Lithography.

A novel main chain scission type photoresists for EUV lithography

G. Vandenberghe, A. Shirotori, M. Hoshino, 2020, Photomask Technology.

Development of main chain scission type photoresists for EUV lithography

G. Vandenberghe, A. Shirotori, M. Hoshino, 2019, Photomask Technology.

EUV resist performance enhancement by UV flood exposure for high NA EUV lithography

Geert Vandenberghe, Makoto Muramatsu, Danilo De Simone, 2021, Advanced Lithography.

The Role of Underlayers in EUVL

Geert Vandenberghe, Danilo De Simone, Alexis Franquet, 2018, Journal of Photopolymer Science and Technology.

Strategies for Increasing the Rate of Defect Annihilation in the Directed Self-Assembly of High-Chi Block Copolymers.

Geert Vandenberghe, C. Grant Willson, Christopher J. Ellison, 2019, ACS applied materials & interfaces.

Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits

Geert Vandenberghe, H.-S. Philip Wong, Wim Dehaene, 2016 .

Evolution of roughness during the pattern transfer of high-chi, 10nm half-pitch, silicon-containing block copolymer structures

Geert Vandenberghe, Chris A. Mack, C. Grant Willson, 2018, Advanced Lithography.

Defect mitigation in sub-20nm patterning with high-chi, silicon-containing block copolymers

Jan Doise, Geert Mannaert, Geert Vandenberghe, 2019, Advanced Lithography.

Readiness of EUV Lithography for Insertion into Manufacturing: The IMEC EUV Program

G. Vandenberghe, I. Pollentier, R. Gronheid, 2013 .

Experimental study of sub-DSA resolution assist features (SDRAF)

Geert Vandenberghe, Hon-Sum Philip Wong, He Yi, 2015, Advanced Lithography.

Application challenges with double patterning technology (DPT) beyond 45 nm

Vincent Wiaux, Geert Vandenberghe, Jo Finders, 2006, SPIE Photomask Technology.

The economic impact of EUV lithography on critical process modules

Geert Vandenberghe, Diederik Verkest, Naoto Horiguchi, 2014, Advanced Lithography.

Design strategy for integrating DSA via patterning in sub-7 nm interconnects

Geert Vandenberghe, H.-S. Philip Wong, Wim Dehaene, 2016, SPIE Advanced Lithography.

The hidden energy tail of low energy electrons in EUV lithography

Geert Vandenberghe, Danilo De Simone, Sergey Babin, 2019, Advanced Lithography.

Impact of DSA process variability on circuit performance

Geert Vandenberghe, Wim Dehaene, Julien Ryckaert, 2016 .

Opportunities and challenges for DSA in logic and memory

Geert Vandenberghe, Julien Ryckaert, Arjun Singh, 2016 .

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

R. Rooyackers, M. Van Hove, K. Ronse, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

EUV Metal Oxide Resist Development Technology for Improved Sensitivity, Roughness and Pattern Collapse Margin for High Volume Manufacturing

G. Vandenberghe, K. Nafus, S. Nagahara, 2022, Journal of Photopolymer Science and Technology.

High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout

K. Ronse, S. Locorotondo, V. Truffert, 2010, 2010 Symposium on VLSI Technology.

Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

R. Rajagopalan, K. Ronse, S. Locorotondo, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).