Yung-Chih Chen

发表

Dynamic Workload Allocation for Edge Computing

Shih-Chieh Chang, Yung-Chih Chen, Yi-Wen Hung, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Dependent-Latch Identification in Reachable State Space

Yung-Chih Chen, Chen-Hsuan Lin, Chun-Yao Wang, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Pattern generation for Mutation Analysis using Genetic Algorithms

Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

A New Necessary Condition for Threshold Function Identification

Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments

Chia-Cheng Wu, Chun-Yao Wang, Shigeru Yamashita, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Optimization of Threshold Logic Networks with Node Merging and Wire Replacement

Yung-Chih Chen, Li-Cheng Zheng, Fu-Lian Wong, 2019, ACM Trans. Design Autom. Electr. Syst..

Optimization of threshold logic networks with ODC-based node merging

Yung-Chih Chen, Fu-Lian Wong, Li-Cheng Zheng, 2018, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Efficient synthesis of approximate threshold logic circuits with an error rate guarantee

Yung-Chih Chen, Chia-Cheng Wu, Chun-Yao Wang, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

In&Out: Restructuring for threshold logic network optimization

Yung-Chih Chen, Chun-Yao Wang, Chia-Chun Lin, 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).

Fast synthesis of threshold logic networks with optimization

Yung-Chih Chen, Yan-Ping Chang, Runyi Wang, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Synthesis for Width Minimization in the Single-Electron Transistor Array

Narayanan Vijaykrishnan, Suman Datta, Yung-Chih Chen, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Width minimization in the Single-Electron Transistor array synthesis

Narayanan Vijaykrishnan, Suman Datta, Yung-Chih Chen, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Rewiring for threshold logic circuit minimization

Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Sensitization criterion for threshold logic circuits and its application

Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model

Chia-Cheng Wu, Juinn-Dar Huang, Chia-Chun Lin, 2021, ACM J. Emerg. Technol. Comput. Syst..

Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays

Suman Datta, Yung-Chih Chen, Chia-Cheng Wu, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Majority logic circuits optimisation by node merging

Yung-Chih Chen, Chia-Cheng Wu, Chun-Yao Wang, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Area-Aware Decomposition for Single-Electron Transistor Arrays

Narayanan Vijaykrishnan, Suman Datta, Yung-Chih Chen, 2016, TODE.

Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays

Narayanan Vijaykrishnan, Suman Datta, Yung-Chih Chen, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays

Narayanan Vijaykrishnan, Suman Datta, Yung-Chih Chen, 2015, The 20th Asia and South Pacific Design Automation Conference.

Verification of Reconfigurable Binary Decision Diagram-Based Single-Electron Transistor Arrays

Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On reconfigurable Single-Electron Transistor arrays synthesis using reordering techniques

Narayanan Vijaykrishnan, Suman Datta, Yung-Chih Chen, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Fast Node Merging With Don't Cares Using Logic Implications

Yung-Chih Chen, Chun-Yao Wang, Yung-Chih Chen, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Dependent latch identification in the reachable state space

Yung-Chih Chen, Chen-Hsuan Lin, Chun-Yao Wang, 2009, 2009 Asia and South Pacific Design Automation Conference.

A Flexible Cluster Tool Simulation Framework with Wafer Batch Dispatching Time Recommendation

Yung-Chih Chen, J. Kung, Yan-Hsiu Liu, 2023, 2023 24th International Symposium on Quality Electronic Design (ISQED).

Novel Probabilistic Combinational Equivalence Checking

Yung-Chih Chen, Chun-Yao Wang, Shih-Chieh Wu, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses

Yung-Chih Chen, Chia-Cheng Wu, Chun-Yao Wang, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Synthesis and verification of cyclic combinational circuits

Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, 2015, 2015 28th IEEE International System-on-Chip Conference (SOCC).

Using structural relations for checking combinationality of cyclic circuits

Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks

Chen-Yu Lin, Chiou-Ting Hsu, Yung-Chih Chen, 2016, IEEE Transactions on Multi-Scale Computing Systems.

Accelerating Binarized Neural Network Inference by Reusing Operation Results and Elevating Resource Utilization on Edge devices

Yung-Chih Chen, Chun-Yao Wang, Yi-Ting Li, 2023, 2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT).

LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach

Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang, 2022, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

LOOPLock: Logic Optimization-Based Cyclic Logic Locking

Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Accuracy Tolerant Neural Networks Under Aggressive Power Optimization

Yung-Chih Chen, Xiang-Xiu Wu, Shih-Chieh Chang, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits

Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Statistic-Based Approach to Testability Analysis

Yung-Chih Chen, Chun-Yao Wang, Chuang-Chi Chiou, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Language-based high level transaction extraction on on-chip buses

Shih-Chieh Chang, Yung-Chih Chen, Chun-Yao Wang, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Fast detection of node mergers using logic implications

Yung-Chih Chen, Chun-Yao Wang, Yung-Chih Chen, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.