Hae-Seung Lee

发表

A 15-b 1-Msample/s digitally self-calibrated pipeline ADC

A. Karanicolas, Hae-Seung Lee, K. L. Barcrania, 1993 .

Superconducting bandpass /spl Delta//spl Sigma/ modulator with 2.23 GHz center frequency and 42.6 GHz sampling rate

Hae-Seung Lee, J. Bulzacchelli, J. Misewich, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

Superconducting Bandpass Modulator With 2.23-GHz Center Frequency and 42.6-GHz Sampling Rate

Hae-Seung Lee, J. Bulzacchelli, 2002 .

Self-calibration technique for A/D converters

D. Hodges, Hae-Seung Lee, 1983 .

Characterization, modeling and minimization of transient threshold voltage shifts in MOSFETs

Hae-Seung Lee, T. Tewksbury, 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

Section 2 Digital Signal Processing

Jacob K. White, A. Lumsdaine, A. Chandrakasan, 2009 .

Noninvasive arterial blood pressure waveform monitoring using two- element ultrasound system

Charles G. Sodini, Hae-Seung Lee, Sabino J. Pietrangelo, 2015, IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control.

Characterization, modeling, and minimization of transient threshold voltage shifts in MOSFETs

T. L. Tewksbury, Hae-Seung Lee, Hae-Seung Lee, 1993 .

A 12b 50MS/s fully differential zero-crossing-based ADC without CMFB

Hae-Seung Lee, L. Brooks, 2009 .

High-Speed Modulators With Reduced Timing

Susan Luschas, Hae-Seung Lee, Hae-Seung Lee, 2002 .

High-speed /spl Sigma//spl Delta/ modulators with reduced timing jitter sensitivity

Susan Luschas, Hae-Seung Lee, Hae-Seung Lee, 2002 .

Comparator-based switched-capacitor circuits for scaled CMOS technologies

Hae-Seung Lee, Charles Sodini, Todd Sepke, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

16-channel oversampled analog-to-digital converter

Hae-Seung Lee, Charles G. Sodini, S. Nadeem, 1994 .

A 12 b , 50 MS / s , Fully Differential Zero-Crossing Based Pipelined

Hae-Seung Lee, 2010 .

13-6 A 12 BIT 600 kSh DIGITALLY SELF-CALIBRATED PIPELINE ALGORITHMIC ADC

Hae-Seung Lee, 2022 .

Motion Tolerant Unfocused Imaging of Physiological Waveforms for Blood Pressure Waveform Estimation Using Ultrasound

C. Sodini, Hae-Seung Lee, Joohyun Seo, 2018, IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control.

SESSION 14: ANALOG PROCESSORS THPM 14.1: A 200MHz CMOS Phase-Locked Loop with Dual Phase Detectors*

Hae-Seung Lee, Charles G. Sodini, Kurt M. Ware, 1989 .

GaN High-Electron Mobility Transistor Track-and-Hold Sampling Circuit With Over 100-dB Signal-to-Noise Ratio

Hae-Seung Lee, T. Palacios, SungWon Chung, 2016, IEEE Electron Device Letters.

Digital post-correction on dynamic nonlinearity in GaN HEMT track-and-hold sampling circuits

Hae-Seung Lee, T. Palacios, SungWon Chung, 2017, 2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS).

Characterization , Modeli : ng , and Minimization of Transient Threshold Vdti ~ ge Shifts h MOSFET ’ s

Hae-Seung Lee, Theodore L. Tewksbury, Hae-Seung Lee, 1994 .

A column-row-parallel ultrasound imaging architecture for 3d plane-wave imaging and Tx 2nd-order harmonic distortion (HD2) reduction

Kailiang Chen, Charles G. Sodini, Kai Thomenius, 2014, 2014 IEEE International Ultrasonics Symposium.

Oversampled pipeline A/D converters with mismatch shaping

Hae-Seung Lee, Ayman Shabra, Hae-Seung Lee, 1998, IEEE J. Solid State Circuits.

Noise Analysis for Comparator-Based Circuits

Hae-Seung Lee, Charles Sodini, Todd Sepke, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning

Song Han, Linxiao Shen, Nan Sun, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

A CMOS-based microdisplay with calibrated backplane

Hae-Seung Lee, A.I. Akinwande, A.R. Chen, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

Adaptive calibration technique for micromachined pressure sensors

Hae-Seung Lee, Charles G. Sodini, Martin A. Schmidt, 1999 .

A 9 b charge-to-digital converter for integrated image sensors

Hae-Seung Lee, S.A. Paul, Hae-Seung Lee, 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

Learning to Design Circuits pdf

Song Han, Hae-Seung Lee, Jiacheng Yang, 2018, ArXiv.

An integrated air-gap-capacitor pressure sensor and digital readout with sub-100 attofarad resolution

Hae-Seung Lee, J. T. Kung, Hae-Seung Lee, 1992 .

A compact, inexpensive apparatus for one-sided etching in KOH and HF

Hae-Seung Lee, Joseph T. Kung, A. Karanicolas, 1991 .

Output impedance requirements for DACs

Hae-Seung Lee, Susan Luschas, Hae-Seung Lee, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

A 5.9-GHz Fully Integrated GaN Frontend Design With Physics-Based RF Compact Model

Hae-Seung Lee, Sushmit Goswami, Li-Shiuan Peh, 2015, IEEE Transactions on Microwave Theory and Techniques.

Non-Invasive Evaluation of a Carotid Arterial Pressure Waveform Using Motion-Tolerant Ultrasound Measurements During the Valsalva Maneuver

Charles G. Sodini, Hae-Seung Lee, Joohyun Seo, 2020, IEEE Journal of Biomedical and Health Informatics.

A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC

Hae-Seung Lee, L. Brooks, Hae-Seung Lee, 2007, IEEE Journal of Solid-State Circuits.

Analog-to-Digital Converters: Digitizing the Analog World

Hae-Seung Lee, Charles Sodini, C. Sodini, 2008, Proceedings of the IEEE.

Interaction of algorithm and implementation for analog VLSI stereo vision

James J. Little, John L. Wyatt, Hae-Seung Lee, 1991, Defense, Security, and Sensing.

A 40 x 40 CCD / CMOS Absolute-Value-of-Difference Processor for Use in a Stereo Vision System

Hae-Seung Lee, Hakkarainen, J. Mikko, 1993 .

A 40*40 CCD/CMOS absolute-value-of-difference processor for use in a stereo vision system

Hae-Seung Lee, J. M. Hakkarainen, Hae-Seung Lee, 1993 .

CMOS resistive fuses for image smoothing and segmentation

John L. Wyatt, P. C. Yu, Charles G. Sodini, 1992 .

S2ADC: A 12-bit, 1.25MS/s Secure SAR ADC with Power Side-Channel Attack Resistance

Anantha P. Chandrakasan, Hae-Seung Lee, Taehoon Jeong, 2020, 2020 IEEE Custom Integrated Circuits Conference (CICC).

S2ADC: A 12-bit, 1.25-MS/s Secure SAR ADC With Power Side-Channel Attack Resistance

Taehoon Jeong, Anantha P. Chandrakasan, Hae-Seung Lee, 2021, IEEE Journal of Solid-State Circuits.

A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC

Hae-Seung Lee, L. Brooks, Hae-Seung Lee, 2009, IEEE Journal of Solid-State Circuits.

A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers

Hae-Seung Lee, Duane S. Boning, Hyun H. Boo, 2015, IEEE Journal of Solid-State Circuits.

15.6 12b 250MS/S pipelined ADC with virtual ground reference buffers

Hae-Seung Lee, Duane S. Boning, Hyun H. Boo, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

Ultrasonic Imaging Transceiver Design for CMUT: A Three-Level 30-Vpp Pulse-Shaping Pulser With Improved Efficiency and a Noise-Optimized Receiver

Hae-Seung Lee, Anantha Chandrakasan, Charles Sodini, 2013, IEEE Journal of Solid-State Circuits.

A Column-Row-Parallel ASIC architecture for 3D wearable / portable medical ultrasonic imaging

Hae-Seung Lee, Charles Sodini, Kailiang Chen, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration

Hae-Seung Lee, Anantha Chandrakasan, Sunghyuk Lee, 2014, IEEE Journal of Solid-State Circuits.

CMOS-based microdisplay with calibrated backplane

Hae-Seung Lee, A. Akinwande, A. Chen, 2005, IEEE Journal of Solid-State Circuits.

Analog VLSI systems for image acquisition and fast early vision processing

Hae-Seung Lee, Tomaso A. Poggio, John L. Wyatt, 1992, International Journal of Computer Vision.

Estimating the Focus of Expansion in Analog VLSI

Hae-Seung Lee, John L. Wyatt, Berthold K. P. Horn, 1998, International Journal of Computer Vision.

A Column-Row-Parallel ASIC Architecture for 3-D Portable Medical Ultrasonic Imaging

Hae-Seung Lee, Charles Sodini, Kailiang Chen, 2016, IEEE Journal of Solid-State Circuits.

Full-speed testing of A/D converters

J. Doernberg, David A. Hodges, H.-S. Lee, 1984 .

A digital readout technique for capacitive sensor applications

R. Howe, J. T. Kung, Hyung-Min Lee, 1988 .

Accuracy considerations in self- calibrating A/D converters

David A. Hodges, Hae-Seung Lee, D. Hodges, 1985 .

Background Calibration of Pipelined ADCs Via Decision Boundary Gap Estimation

Hae-Seung Lee, Lane Brooks, Hae-Seung Lee, 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies

Hae-Seung Lee, P. Holloway, T. Sepke, 2006, IEEE Journal of Solid-State Circuits.

A 2.5 V 12 b 5 MSample/s pipelined CMOS ADC

Hae-Seung Lee, P.C. Yu, Hae-Seung Lee, 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.