R. Scheuerlein

A substrate-plate trench-capacitor (SPT) memory cell for dynamic RAM's

D. Critchlow, P. Cottrell, N. Lu, 1986 .

A 130.7-$\hbox{mm}^{2}$ 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology

Masahide Matsumoto, Hirofumi Inoue, Takeshi Yamaguchi, 2014, IEEE Journal of Solid-State Circuits.

A 14-ns 14-Mb CMOS DRAM with 300-mW active power

R. Scheuerlein, T. Kirihata, K. Hosokawa, 1992 .

Exchange-biased magnetic tunnel junctions and application to nonvolatile magnetic random access memory (invited)

William J. Gallagher, Yu Lu, Eugene J. O'Sullivan, 1999 .

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

Yasunao Katayama, W. H. Henkels, Toshiaki Kirihata, 1989 .

Magnetization Reversal in Micron-Sized Magnetic Thin Films

William J. Gallagher, Yu Lu, Philip Louis Trouilloud, 1998 .

A 10 ns read and write non-volatile memory array using a magnetic tunnel junction and FET switch in each cell

R. Scheuerlein, W. Gallagher, S. Parkin, 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

Memories of tomorrow

Yu Lu, R. P. Robertazzi, William J. Gallagher, 2002 .

Offset word line architecture for scaling DRAMs to the Gigabit level

J. D. Meindl, R. E. Scheuerlein, J. Meindl, 1987, 1987 Symposium on VLSI Circuits.