Yuichi Nakamura

发表

Fine-grained power gating based on the controlling value of logic gates (VLSI設計技術)

Takashi Horiyama, Lei Chen, Shinji Kimura, 2008 .

A dynamic programming method for single machine scheduling

T. Ibaraki, Yuichi Nakamura, 1994 .

Logic Synthesis with AND and OR Gates in Multi-levels

Saburo Muroga, Yuichi Nakamura, S. Muroga, 2000, The VLSI Handbook.

Revisiting rendezvous protocols in the context of RDMA-capable host channel adapters and many-core processors

Yutaka Ishikawa, Yuichi Nakamura, Atsushi Hori, 2013, EuroMPI.

Budgeting-free hierarchical design method for large scale and high-performance LSIs

Takumi Okamoto, Yuichi Nakamura, Ko Yoshikawa, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems

Yuichi Nakamura, Yasuhiro Takashima, Masato Inagi, 2010, IPSJ Trans. Syst. LSI Des. Methodol..

ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems

Atsushi Takahashi, Yuichi Nakamura, Yasuhiro Takashima, 2008, 2008 IEEE International Symposium on Circuits and Systems.

A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os

Yoji Kajitani, Yuichi Nakamura, Yasuhiro Takashima, 2006, 2006 IEEE International Conference on Field Programmable Technology.

FPGA-accelerated complex event processing

Takashi Takenaka, Hiroaki Inoue, Yuichi Nakamura, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Future trend of deep learning frameworks — From the perspective of big data analytics and HPC

Takuya Araki, Yuichi Nakamura, Yuichi Nakamura, 2017, 2017 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC).

Fast optical channel recovery in field demonstration of 100-Gbit/s Ethernet over OTN using real-time DSP.

Shogo Yamanaka, Eiji Yoshida, Yoshiaki Kisaka, 2011, Optics express.

A Study of Multi-core Processor Design with Asynchronous Interconnect Using Synchronous Design Tools

Yuichi Nakamura, Katsunori Tanaka, Atsushi Atarashi, 2008, IPSJ Trans. Syst. LSI Des. Methodol..

A hardware/software co-simulation environment for micro-processor design with HDL simulator and OS interface

Yuichi Nakamura, Yoshiyuki Ito, Yuichi Nakamura, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems

Yuichi Nakamura, Yasuhiro Takashima, Masato Inagi, 2009, 2009 International Conference on Field Programmable Logic and Applications.

Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems

Atsushi Takahashi, Yuichi Nakamura, Yasuhiro Takashima, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[Invited Talk] HW/SW Co-verification Method using FPGAs

Yuichi Nakamura, Kouhei Hosokawa, Kouhei Hosokawa, 2008 .

Fine-Grained Power Gating Based on the Controlling Value of Logic Elements

Takashi Horiyama, Lei Chen, Shinji Kimura, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A fast hardware/software co-verification method for systern-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication

Yuichi Nakamura, T. Yoshimura, I. Kuroda, 2004, Proceedings. 41st Design Automation Conference, 2004..

Domino Logic Synthesis System and its Applications

Takeshi Yoshimura, Yuichi Nakamura, Yasuhiko Hagihara, 2006, J. Circuits Syst. Comput..