T. Hook

发表

Terence B. Hook, Atsushi Moriwaki, Matthew J. Breitwisch, 2003, IBM J. Res. Dev..

Enhanced multi-threshold (MTCMOS) circuits using variable well bias

S. Kosonocky, P. Cottrell, T. Hook, 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

High performance and low power transistors integrated in 65nm bulk CMOS technology

M. Weybright, A. Vayshenker, A. Steegen, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering

D. Lea, E. Nowak, S. Yang, 2003, IEEE International Electron Devices Meeting 2003.

Channel Length and Threshold Voltage Dependence of Transistor Mismatch in a 32-nm HKMG Technology

T. Hook, G. Tsutsui, Jeffrey B. Johnson, 2010, IEEE Transactions on Electron Devices.

'System on a chip' technology platform for 0.18 /spl mu/m digital, mixed signal and eDRAM applications

B. Flietner, R. Hannon, S. Iyer, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

High-performance logic and high-gain analog CMOS transistors formed by a shadow-mask technique with a single implant step

M. Breitwisch, D. Hoyniak, R. Mann, 2002 .

Lateral ion implant straggle and mask proximity effect

J. Johnson, D. Hoyniak, P. Cottrell, 2003 .

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

T. Adam, T. Standaert, M. Khare, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

D. Corliss, T. Standaert, R. Wong, 2017, 2017 Symposium on VLSI Technology.

Transistor Matching and Fin Angle Variation in FinFET Technology

T. Hook, K. McStay, Samarth Agarwal, 2015, IEEE Transactions on Electron Devices.

Plasma charging damage in SOI technology

A. Chou, M. Khare, J. Gambino, 2001, 2001 6th International Symposium on Plasma- and Process-Induced Damage (IEEE Cat. No.01TH8538).

Detection of thin oxide (3.5 nm) dielectric degradation due to charging damage by rapid-ramp breakdown

Terence B. Hook, Chuan Lin, T. Hook, 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).

Channel Material Dependence of Wave Function Deformation Scattering in Ultrascaled FinFETs

T. Hook, M. Vaidyanathan, K. Holland, 2017, IEEE Transactions on Electron Devices.

Gate-Induced-Drain-Leakage Current in 45-nm CMOS Technology

R. Lindsay, D. Ahlgren, E. Zhao, 2008, IEEE Transactions on Device and Materials Reliability.

Mechanism and process dependence of negative bias temperature instability (NBTI) for pMOSFETs with ultrathin gate dielectrics

M. Khare, T. Ning, T. Hook, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Analysis and Modeling of Threshold Voltage Mismatch for CMOS at 65 nm and Beyond

T. Hook, J.B. Johnson, Yoo-mi Lee, 2008, IEEE Electron Device Letters.

Mechanism of Threshold Voltage Shift (ΔVth) Caused by Negative Bias Temperature Instability (NBTI) in Deep Submicron pMOSFETs

Zhijian Yang, T. Hook, C. Wann, 2002 .

Channel length dependence of random telegraph signal in sub-micron MOSFET's

T. Ma, T. Hook, Ming-Horn Tsai, 1994, IEEE Electron Device Letters.

3-D LER and RDF Matching Performance of Nanowire FETs in Inversion, Accumulation, and Junctionless Modes

T. Hook, A. Dixit, C. Gupta, 2018, IEEE Transactions on Electron Devices.

Transistor Mismatch Properties in Deep-Submicrometer CMOS Technologies

Hyunwoo Lee, Myung-Hee Na, Xiaobin Yuan, 2011, IEEE Transactions on Electron Devices.

Electron trapping, nitride conduction, and forward gain instability in a lateral p-n-p device

T. Hook, A. Ferris-Prabhu, M. Johnson, 1990 .

Series Resistance Reduction With Linearity Assessment for Vertically Stacked Junctionless Accumulation Mode Nanowire FET

M. Kumar, T. Hook, A. Dixit, 2018, IEEE Transactions on Electron Devices.

Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs

T. B. Hook, T. Yamashita, T. E. Standaert, 2013, 2013 IEEE International Electron Devices Meeting.

Channel doping impact on FinFETs for 22nm and beyond

P. Oldiges, T. B. Hook, T. Yamashita, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Advanced FDSOI Device Design: The U-Channel Device for 7 nm Node and Beyond

R. Dennard, T. Hook, R. Muralidhar, 2018, IEEE Journal of the Electron Devices Society.

Anomalous Dependence of Threshold Voltage Mismatch of Short-Channel Transistors

T. Hook, J. Johnson, J. Shah, 2011, IEEE Transactions on Electron Devices.

Nanowire FET design for 7-nm SOI-CMOS technology

T. Hook, A. Dixit, A. Bansal, 2015, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Interface state generation in pFETs with ultra-thin oxide and oxynitride on (100) and (110) Si substrates

Terence B. Hook, James H. Stathis, Ronald J. Bolam, 2005 .

Dual gate oxide charging damage in damascene copper technologies

A. Chou, T. Hook, A. Stamper, 2000, 2000 5th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.00TH8479).

(Invited) Silicon Germanium FinFET Device Physics, Process Integration and Modeling Considerations

Pierre Morin, Ali Khakifirooz, Bruce B. Doris, 2014 .

Impact of Line and Via Resistance on Device Performance at the 5nm Gate All Around Node and Beyond

T. Hook, L. Clevenger, N. Lanzillo, 2018, 2018 IEEE International Interconnect Technology Conference (IITC).

Impact of Hot-Carrier Degradation on Drain-Induced Barrier Lowering in Multifin SOI n-Channel FinFETs With Self-Heating

T. Hook, R. Vega, A. Dixit, 2020, IEEE Transactions on Electron Devices.

Series Resistance Reduction in Stacked Nanowire FETs for 7-nm CMOS Technology

T. Hook, A. Dixit, A. Bansal, 2016, IEEE Journal of the Electron Devices Society.

Characterization and analysis of gate-induced-drain-leakage current in 45 nm CMOS technology

R. Lindsay, D. Ahlgren, E. Zhao, 2007, 2007 IEEE International Integrated Reliability Workshop Final Report.

Process-induced damage in a dual-oxide (3.5/6.8 nm) 0.18-/spl mu/m copper CMOS technology

T. Hook, 1999, 1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395).

Reliability issues for silicon-on-insulator

M. Khare, D. Badami, T. Hook, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

The effect of fluorine in an advanced CMOS process with triple (1.6/2.2/5.2 nm) nitrided gate oxide

T. Hook, R. Kontra, J. Burnham, 2003, 2003 8th International Symposium Plasma- and Process-Induced Damage..

Impact of Short-Wavelength and Long-Wavelength Line-Edge Roughness on the Variability of Ultrascaled FinFETs

T. Hook, M. Vaidyanathan, K. Holland, 2017, IEEE Transactions on Electron Devices.

Implant approaches and challenges for 20nm node and beyond ETSOI devices

M. Khare, S. Luning, B. Haran, 2011, IEEE 2011 International SOI Conference.

Power and Technology Scaling into the 5 nm Node with Stacked Nanosheets

Terence B. Hook, T. Hook, 2017 .

Titanium silicide/silicon nonohmic contact resistance for NFET's, PFET's, diffused resistors, and NPN's in a BiCMOS technology

E. Nowak, R. Mann, T. Hook, 1995 .

Toward Microwave S- and X-Parameter Approaches for the Characterization of Ferroelectrics for Applications in FeFETs and NCFETs

P. Solomon, T. Hook, M. Vaidyanathan, 2019, IEEE Transactions on Electron Devices.

Evaluation of 10-nm Bulk FinFET RF Performance—Conventional Versus NC-FinFET

Y. Chauhan, T. Hook, R. Vega, 2018, IEEE Electron Device Letters.

Switching-Speed Limitations of Ferroelectric Negative-Capacitance FETs

Terence B. Hook, Prasad S. Gudem, Shahriar Rizwan, 2016, IEEE Transactions on Electron Devices.

Plasma process-induced damage on thick (6.8 nm) and thin (3.5 nm) gate oxide: parametric shifts, hot-carrier response, and dielectric integrity degradation

Terence B. Hook, Chuan Lin, David Harmon, 2001, Microelectron. Reliab..

Backside films and charging during via etch in LOCOS and STI technologies

T. Hook, 1998, 1998 3rd International Symposium on Plasma Process-Induced Damage (Cat. No.98EX100).

A CMOS Technology for a Sub-5-ns 3.3-V LVTTL 1-Mbit SRAM

E. Nowak, K. Watson, T. Hook, 1995, ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference.

Comparison of heat outflow in dense sub-14nm contemporary NFETs: Bulk/SOI, inserted-oxide FinFET and nanowire FET

T. Hook, A. Dixit, Anshul Gupta, 2016, 2016 3rd International Conference on Emerging Electronics (ICEE).

7-nm Nanowire FET process variation modeling using industry standard BSIM-CMG model

Terence B. Hook, Ramendra Singh, Abhisek Dixit, 2016, 2016 3rd International Conference on Emerging Electronics (ICEE).

Reliable airgap BEOL technology in advanced 48 nm pitch copper/ULK interconnects for substantial power and performance benefits

S. Gates, D. Edelstein, T. Hook, 2017, 2017 IEEE International Interconnect Technology Conference (IITC).

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

D. Liu, P. Oldiges, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

B. Lherron, D. Chanemougame, P. Oldiges, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

The combined effects of deuterium anneals and deuterated barrier-nitride processing on hot-electron degradation in MOSFET's

Terence B. Hook, Jay Burnham, Steven W. Mittl, 1999 .

Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond

Phil Oldiges, Terence Hook, Myung-Hee Na, 2015, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

P. Oldiges, C. Park, N. Loubet, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below

O. Rozeau, O. Faynot, M. Vinet, 2012, 2012 International Electron Devices Meeting.

Effects of trap-assisted tunneling on gate-induced drain leakage in silicon–germanium channel p-type FET for scaled supply voltages

T. Hook, D. Nair, R. Divakaruni, 2016 .

The effects of fluorine on parametrics and reliability in a 0.18-/spl mu/m 3.5/6.8 nm dual gate oxide CMOS technology

Terence B. Hook, Nivo Rovedo, Klaus Schruefer, 2001 .

Effects and prevention of source/drain ion implantation into the polysilicon in a BiCMOS technology

T. Hook, J. Piccirillo, Christa R. Willets, 1995 .

T. Hook, 1990 .

Modeling of Effective Thermal Resistance in Sub-14-nm Stacked Nanowire and FinFETs

Terence B. Hook, Abhisek Dixit, Ishita Jain, 2018, IEEE Transactions on Electron Devices.

An analytical formulation of the peripheral base resistance with application to statistical process variations

Terence B. Hook, T. Hook, 1990 .

A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs

S. Narasimha, J. Johnson, M. Khare, 2015, Symposium on VLSI Technology.

Challenges and Opportunities for Stacked Transistor: DTCO and Device

A. Young, B. Haran, T. Hook, 2021, Symposium on VLSI Technology.

Accurate performance evaluation for the horizontal nanosheet standard-cell design space beyond 7nm technology

L. Liebmann, Y. M. Lee, M. H. Na, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Nonrandom Device Mismatch Considerations in Nanoscale SRAM

Benton H. Calhoun, Randy W. Mann, Terry B. Hook, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Impact of back bias on ultra-thin body and BOX (UTBB) devices

M. Vinet, T. Skotnicki, L. Grenouillet, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Process stability of deuterium-annealed MOSFET's

W.F. Clark, K. Watson, T. Hook, 1999, IEEE Electron Device Letters.

Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT

Jie Yang, Terence B. Hook, Andreas Knorr, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Comment on “Channel Length and Threshold Voltage Dependence of a Transistor Mismatch in a 32-nm HKMG Technology”

Terence B. Hook, Gerard Ghibaudo, Jeffrey B. Johnson, 2011 .

Fully depleted devices for designers: FDSOI and FinFETs

Terence B. Hook, T. Hook, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.