A. Ono

TED control technology for suppression of reverse narrow channel effect in 0.1 /spl mu/m MOS devices

A. Ono, R. Ueno, I. Sakai, 1997, International Electron Devices Meeting. IEDM Technical Digest.

A 0.13 /spl mu/m CMOS technology integrating high-speed and low-power/high-density devices with two different well/channel structures

A. Ono, K. Imai, K. Noda, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

A 0.18 /spl mu/m fully depleted CMOS on 30 nm thick SOI for sub-1.0 V operation

K. Yamaguchi, A. Ono, K. Imai, 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

Radical nitridation in multi-oxide process for 100 nm generation CMOS technology

A. Ono, Y. Yasuda, K. Fukasaku, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

TP 12.7 A 500MHz 32b 0.4pm CMOS RISC Processor LSI

Masahiro Nomura, Takashi Nakayama, H. Yamada, 1993 .

A Novel Via-fuse Technology Featuring Highly Stable Blow Operation with Large On-off Ratio for 32nm Node and Beyond

A. Ono, H. Takaoka, H. Tsuda, 2007, 2007 IEEE International Electron Devices Meeting.

A Novel Cu Electrical Fuse Structure and Blowing Scheme Utilizing Crack-Assisted Mode for 90-45nm-Node and Beyond

Y. Kobayashi, M. Hamada, T. Ueda, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..