I. Chen

发表

Subbreakdown drain leakage current in MOSFET

T. Chan, C. Hu, J. Chen, 1987, IEEE Electron Device Letters.

A shallow trench isolation study for 0.25/0.18 /spl mu/m CMOS technologies and beyond

I. Chen, A. Chatterjee, J. Esquivel, 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

Oxide thickness dependence of inverter delay and device reliability for 0.25 /spl mu/m CMOS technology

R. Chapman, I. Chen, A. Chatterjee, 1993, Proceedings of IEEE International Electron Devices Meeting.

Dynamic stressing of thin oxides

C. Hu, S. Holland, I. Chen, 1986, 1986 International Electron Devices Meeting.

High performance sub-half micron CMOS using rapid thermal processing

R. Chapman, W. Richardson, I. Chen, 1991, International Electron Devices Meeting 1991 [Technical Digest].

A sub-0.1 /spl mu/m gate length CMOS technology for high performance (1.5 V) and low power (1.0 V)

I. Chen, S. Aur, Q. Hong, 1996, International Electron Devices Meeting. Technical Digest.

A 0.10 /spl mu/m gate length CMOS technology with 30 /spl Aring/ gate dielectric for 1.0 V-1.5 V applications

I. Chen, D. Rogers, A. Amerasekera, 1997, International Electron Devices Meeting. IEDM Technical Digest.

A scaled 1.8 V, 0.18 /spl mu/m gate length CMOS technology: device design and reliability considerations

I. Chen, M. Rodder, S. Aur, 1995, Proceedings of International Electron Devices Meeting.

A quantitative physical model for time-dependent breakdown in SiO2

S. Holland, S. Holland, I. Chen, 1985, 23rd International Reliability Physics Symposium.

A shallow trench isolation using LOCOS edge for preventing corner effects for 0.25/0.18 /spl mu/m CMOS technologies and beyond

A. Chatterjee, D. Rogers, I. Ali, 1996, International Electron Devices Meeting. Technical Digest.

Shallow trench isolation for advanced ULSI CMOS technologies

I. Chen, A. Chatterjee, K. Joyner, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Electron-trap generation by recombination of electrons and holes in SiO2

Chenming Hu, Stephen E. Holland, C. Hu, 1987 .

On physical models for gate oxide breakdown

T. Ma, C. Hu, S. Holland, 1984, IEEE Electron Device Letters.

Electrical breakdown in thin gate and tunneling oxides

Ih-Chin Chen, Chenming Hu, Stephen E. Holland, 1985 .

TDDB on poly-gate single doping type capacitors

Ih-Chin Chen, I. Chen, H. Tigelaar, 1992, 30th Annual Proceedings Reliability Physics 1992.

Polycrystalline In–Ga–O Thin-Film Transistors Coupled With a Nitrogen Doping Technique for High-Performance UV Detectors

I. Chen, S. Chang, Sheng-Po Chang, 2020, IEEE Transactions on Electron Devices.

The effect of channel hot carrier stressing on gate oxide integrity in MOSFET

T. Chan, C. Hu, I. Chen, 1988, 26th Annual Proceedings Reliability Physics Symposium 1988.

A comparison of TiN processes for CVD W/TiN gate electrode on 3 nm gate oxide

G.A. Brown, J. D. Luttmer, R. Chapman, 1997, International Electron Devices Meeting. IEDM Technical Digest.

CMOS metal replacement gate transistors using tantalum pentoxide gate insulator

G.A. Brown, A. Chatterjee, M. Rodder, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Interface trap-enhanced gate-induced leakage current in MOSFET

C.W. Teng, D.J. Coleman, I. Chen, 1989, IEEE Electron Device Letters.

Conduction mechanisms in sputtered Ta2O5 on Si with an interfacial SiO2 layer

S. Banerjee, I. Chen, R. Doering, 1989 .

A high quality high temperature compatible Tantalum oxide film for advanced dRAM applications

I. Chen, S. Banerjee, G.A. Brown, 1987, 1987 International Electron Devices Meeting.

Reliability of Submicron Mosfet's with Deposited Gate Oxides under F-N Injection and Hot-Carrier Stress

Jack C. Lee, I. Chen, M. Hao, 1992 .

Ultra-thin silicon-dioxide breakdown characteristics of MOS devices with n+and p+polysilicon gates

Chenming Hu, S. Holland, S. Holland, 1987, IEEE Electron Device Letters.

Substrate hole current and oxide breakdown

Chenming Hu, Stephen E. Holland, C. Hu, 1986 .

Accelerated testing of time-dependent breakdown of SiO2

I. Chen, I.C. Chen, C. Hu, 1987, IEEE Electron Device Letters.

Comparison between CVD and thermal oxide dielectric integrity

C. Hu, I. Chen, J. Lee, 1986, IEEE Electron Device Letters.

Physical oxide thickness extraction and verification using quantum mechanical simulation

G. Klimeck, A. Chatterjee, Gerhard Klimeck, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Hole trapping and breakdown in thin SiO2

S. Holland, C. Hu, S. Holland, 1986, IEEE Electron Device Letters.

Comparative evaluation of gap-fill dielectrics in shallow trench isolation for sub-0.25 /spl mu/m technologies

S. Aur, A. Chatterjee, I. Ali, 1996, International Electron Devices Meeting. Technical Digest.

Accelerated testing of silicon dioxide wearout

C. Hu, I. Chen, J. Lee, 1987, 1987 Symposium on VLSI Technology.

The Structures of Tantalum Pentoxide Film Formed by Reactive DC Magnetron Sputter-Deposition of Ta

I. Chen, J. A. Keenan, P. Chang, 1988 .

Low resistance Ti or Co salicided raised source/drain transistors for sub-0.13 /spl mu/m CMOS technologies

M. Nandakumar, J. Kittl, K. Violette, 1997, International Electron Devices Meeting. IEDM Technical Digest.

CoSi/sub 2/ with low diode leakage and low sheet resistance at 0.065 /spl mu/m gate length

J. Kittl, H. Tsai, I. Chen, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Oxide breakdown dependence on thickness and hole current - enhanced reliability of ultra thin oxides

S. Holland, C. Hu, S. Holland, 1986, 1986 International Electron Devices Meeting.

Oxide Defect Density, Failue Rate and Screen Yield

C. Hu, S. Holland, I. Chen, 1986, 1986 Symposium on VLSI Technology. Digest of Technical Papers.

Effects of poly depletion on the estimate of thin dielectric lifetime

S.J. Wang, I. Chen, H. Tigelaar, 1991, IEEE Electron Device Letters.

Shallow source/drain extension formation using antimony and indium pre-amorphization schemes for 0.18- to 0.13-μm CMOS technologies

Ih-Chin Chen, J. C. Hu, Mark S. Rodder, 1997, Advanced Lithography.

A quantitative physical model for the band-to-band tunneling-induced substrate hot electron injection in MOS devices

Ih-Chin Chen, I. Chen, Clarence W. Teng, 1992 .

Feasibility of using W/TiN as metal gate for conventional 0.13 /spl mu/m CMOS technology and beyond

A. Chatterjee, M. Rodder, R. Chapman, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Applicability of RTCVD and LPCVD nitride spacers for sub-0.18-μm CMOS technologies

Wei-Tsun Shiau, Jerry C. Hu, Mark Rodder, 1997, Advanced Lithography.

Optimizing state-of-the-art 28nm core/SRAM device performance by cryo-implantation technology

T. Y. Lu, C. I. Li, Y. S. Huang, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

Mitigating eSiGe strain relaxation using cryo-implantation technology for PSD formation

C. I. Li, J. Y. Wu, I. Chen, 2011, 11th International Workshop on Junction Technology (IWJT).

Highly-selective superconformai CVD Ti silicide process enabling area-enhanced contacts for next-generation CMOS architectures

H. van Meer, J. Jordan-Sweet, W. Wang, 2017, 2017 Symposium on VLSI Technology.

Simple gate-to-drain overlapped MOSFETs using poly spacers for high immunity to channel hot-electron degradation

I. Chen, C. Wei, C. Teng, 1990, IEEE Electron Device Letters.

Scalability of a trench capacitor cell for 64 Mbit DRAM

C.W. Teng, D.J. Coleman, I. Chen, 1989, International Technical Digest on Electron Devices Meeting.