T. Houston

A shallow trench isolation study for 0.25/0.18 /spl mu/m CMOS technologies and beyond

I. Chen, A. Chatterjee, J. Esquivel, 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

Model for CMOS/SOI single-event vulnerability

M. Alles, T. Houston, L. Massengill, 1989 .

Behavior of indium in thin SOI films

K. Joyner, T. Houston, J. B. Jacobs, 1997, 1997 IEEE International SOI Conference Proceedings.

Isolation techniques for 256 Mbit SOI DRAM application

Theodore W. Houston, Yin Hu, Clarence W. Teng, 1995, 1995 IEEE International SOI Conference Proceedings.

Ultra-thin film SOI/CMOS with selective-epi source/drain for low series resistance, high drive current

T. Houston, R. Wise, Jeong-Mo Hwang, 1994, Proceedings of 1994 VLSI Technology Symposium.

Considerations for the design of an SRAM with SOI technology

T. W. Houston, T. Houston, 1987, IEEE Circuits and Devices Magazine.

Radiation Hardness of a Silicon MESFET 4K × 1 sRAM

T. Houston, W. Shedd, L. Hite, 1984, IEEE Transactions on Nuclear Science.

A 553 K-transistor LISP processor chip

Theodore W. Houston, K. N. Ruparel, S. Lusky, 1987 .

Fabrication and performance of submicron silicon MESFET

G. Taylor, T. Houston, H. Darley, 1978, 1978 International Electron Devices Meeting.

A 65 nm CMOS technology for mobile and digital signal processing applications

D. Mosher, H. Mair, D. Scott, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..