D. K. Vries

Investigation of gross die per wafer formulas

D. K. de Vries, D. K. Vries, 2005 .

Quasi-one-dimensional ballistic electron transport in in-plane-gated channels at liquid nitrogen temperature

D. K. Vries, K. Ploog, A. Wieck, 1994 .

In‐plane‐gate transistors fabricated from Si/SiGe heterostructures by focused ion beam implantation

D. K. Vries, G. Abstreiter, F. Schäffler, 1995 .

A dynamical approach to time dilation and length contraction

D. K. Vries, W. M. Muynck, 1996 .

Lateral electron depletion in focused-ion-beam implanted pseudomorphic heterostructures with InxGa1−xAs channels

D. K. Vries, A. Wieck, K. Ploog, 1996 .

Potential distribution in the van der Pauw technique

D. K. Vries, A. Wieck, 1995 .

Intrinsic and extrinsic capacitances of in‐plane‐gated transistors

D. K. Vries, A. Wieck, P. Stelmaszyk, 1996 .

Methods to quantify the detection probability of killing defects

D. K. de Vries, D. K. Vries, 2005 .

Calibration of open interconnect yield models

Dirk K. de Vries, Paul L. C. Simon, D. K. Vries, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.