C. Yeo

Fabrication and characteristics of novel load PMOS SSTFT (Stacked Single-crystal Thin Film Transistor) for 3-Dimensional SRAM memory cell

K. Kim, K. Kwak, B. Hwang, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

High Speed and Highly Cost effective 72M bit density S3 SRAM Technology with Doubly Stacked Si Layers, Peripheral only CoSix layers and Tungsten Shunt W/L Scheme for Standalone and Embedded Memory

Kinam Kim, Soon-Moon Jung, K. Kwak, 2007, 2007 IEEE Symposium on VLSI Technology.

Low-Temperature Solid Phase Epitaxial Regrowth of Silicon for Stacked Static Random Memory Application

J. Moon, Soon-Moon Jung, C. Yeo, 2011 .

Highly Manufacturable 7th Generation 3D NAND Flash Memory with COP structure and Double Stack Process

Sungjin Ahn, Y. Shin, C. Yeo, 2021, 2021 Symposium on VLSI Technology.