A. Nainani

发表

Development of high-k dielectric for antimonides and a sub 350°C III–V pMOSFET outperforming Germanium

J. B. Boos, K. Saraswat, Y. Nishi, 2010, 2010 International Electron Devices Meeting.

Experimental demonstration of high mobility Ge NMOS

K. Saraswat, H. Wong, A. Nainani, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

GeSn technology: Extending the Ge electronics roadmap

K. Saraswat, Y. Nishi, A. Nainani, 2011, 2011 International Electron Devices Meeting.

Contact resistivity reduction through interfacial layer doping in metal-interfacial layer-semiconductor contacts

P. P. Manik, A. Nainani, S. Lodha, 2013 .

Optimal design of III–V heterostructure MOSFETs

K. Saraswat, A. Nainani, Ze Yuan, 2010, 2010 International Conference on Simulation of Semiconductor Processes and Devices.

High-Mobility Ge N-MOSFETs and Mobility Degradation Mechanisms

Duygu Kuzum, Aneesh Nainani, Tejas Krishnamohan, 2011, IEEE Transactions on Electron Devices.

Increase in current density for metal contacts to n-germanium by inserting TiO2 interfacial layer to reduce Schottky barrier height

K. Saraswat, A. Nainani, Yun Sun, 2011 .

Understanding device impact of line edge/width roughness in frequency domain

Peng Xie, He Ren, Huixiong Dai, 2013, Advanced Lithography.

Cryo implanted high performance n+/p junctions in Ge for future CMOS

A. Nainani, S. Lodha, C. Hatem, 2014, Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Germanium oxynitride gate interlayer dielectric formed on Ge(100) using decoupled plasma nitridation

A. Nainani, S. Lodha, S. Kothari, 2013 .

Nickel germanide with rare earth interlayers for Ge CMOS applications

A. Nainani, S. Lodha, S. Ganguly, 2013, 2013 IEEE International Conference of Electron Devices and Solid-state Circuits.

Enhancement of Phosphorus Dopant Activation and Diffusion Suppression by Fluorine Co-Implant in Epitaxially Grown Germanium

K. Saraswat, A. Nainani, W. Jung, 2012, 2012 International Silicon-Germanium Technology and Device Meeting (ISTDM).

Impact of fixed charge on metal-insulator-semiconductor barrier height reduction

H.-S. Philip Wong, Krishna C. Saraswat, Aneesh Nainani, 2011 .

Enhancing hole mobility in III-V semiconductors

J. B. Boos, K. Saraswat, A. Nainani, 2011, 1108.5507.

Development of A 3D Simulator for Metal Nanocrystal (NC) Flash Memories under NAND Operation

S. Mahapatra, U. Ganguly, J. Vasi, 2007, 2007 IEEE International Electron Devices Meeting.

Fermi-level unpinning and low resistivity in contacts to n-type Ge with a thin ZnO interfacial layer

P. P. Manik, A. Nainani, S. Lodha, 2012 .

High performance germanium n-MOSFET with antimony dopant activation beyond 1×1020 cm−3

Y. Nishi, R. Brennan, S.-L. Cheng, 2010, 2010 International Electron Devices Meeting.

Fluorine passivation of vacancy defects in bulk germanium for Ge metal-oxide-semiconductor field-effect transistor application

K. Saraswat, A. Nainani, Jin-Hong Park, 2012 .

Schottky barrier height reduction for metal/n-GaSb contact by inserting TiO2 interfacial layer with low tunneling resistance

K. Saraswat, A. Nainani, Ze Yuan, 2011 .

ZnO: an attractive option for n-type metal-interfacial layer-semiconductor (Si, Ge, SiC) contacts

A. Nainani, S. Lodha, S. Gupta, 2012, 2012 Symposium on VLSI Technology (VLSIT).

High Performance 400 °C p+/n Ge Junctions Using Cryogenic Boron Implantation

A. Nainani, S. Lodha, C. Hatem, 2014, IEEE Electron Device Letters.

Hole Mobility and Its Enhancement with Strain for Technologically Relevant III-V Semiconductors

K. Saraswat, A. Nainani, T. Krishnamohan, 2009, 2009 International Conference on Simulation of Semiconductor Processes and Devices.

Optimization of the $\hbox{Al}_{2}\hbox{O}_{3}/ \hbox{GaSb}$ Interface and a High-Mobility GaSb pMOSFET

J. B. Boos, K. Saraswat, Y. Nishi, 2011, IEEE Transactions on Electron Devices.

Optimization of the Al 2 O 3 / GaSb Interface and a High-Mobility GaSb pMOSFET

K. Saraswat, Y. Nishi, T. Irisawa, 2011 .

Amelioration of interface state response using band engineering in III-V quantum well metal-oxide-semiconductor field-effect transistors

J. B. Boos, K. Saraswat, A. Nainani, 2012 .

InxGa1-xSb channel p-metal-oxide-semiconductor field effect transistors: Effect of strain and heterostructure design

Krishna C. Saraswat, Mario G. Ancona, J. B. Boos, 2011 .

Device quality Sb-based compound semiconductor surface: A comparative study of chemical cleaning

J. B. Boos, K. Saraswat, T. Irisawa, 2011 .

Antimonide-Based Heterostructure p-Channel MOSFETs With Ni-Alloy Source/Drain

J. B. Boos, K. Saraswat, A. Nainani, 2013, IEEE Electron Device Letters.

Heterostructure design and demonstration of InGaSb channel III-V CMOS transistors

J. B. Boos, K. Saraswat, A. Nainani, 2011, 2011 International Semiconductor Device Research Symposium (ISDRS).

Addressing key challenges in 1T-DRAM: Retention time, scaling and variability — Using a novel design with GaP source-drain

Krishna C. Saraswat, Ashish Pal, Aneesh Nainani, 2013, 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

Is strain engineering scalable in FinFET era?: Teaching the old dog some new tricks

A. Brand, Er-Xuan Ping, K. Schuegraf, 2012, 2012 International Electron Devices Meeting.

on-State Performance Enhancement and Channel-Direction-Dependent Performance of a Biaxial Compressive Strained $ \hbox{Si}_{0.5}\hbox{Ge}_{0.5}$ Quantum-Well pMOSFET Along $ \langle \hbox{110} \rangle$ and $\langle \hbox{100} \rangle$ Channel Directions

Leonard Franklin Register, Raj Jammy, Aneesh Nainani, 2011, IEEE Transactions on Electron Devices.

Study of piezoresistance under unixial stress for technologically relevant III-V semiconductors using wafer bending experiments

K. Saraswat, A. Nainani, P. Majhi, 2010 .