K. Zawadzki

Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology

C. Auth, A. Murthy, R. Shaheed, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

R. Chau, C. Auth, M. Bost, 2007, 2007 IEEE International Electron Devices Meeting.

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

C. Auth, M. Bost, V. Chikarmane, 2012, 2012 Symposium on VLSI Technology (VLSIT).

High performance Hi-K + metal gate strain enhanced transistors on (110) silicon

R. Kotlyar, A. Murthy, C. Weber, 2008, 2008 IEEE International Electron Devices Meeting.

A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

M. Silberstein, C. Auth, M. Bost, 2003, IEEE International Electron Devices Meeting 2003.

Understanding stress enhanced performance in Intel 90nm CMOS technology

R. Kotlyar, P. Matagne, C. Auth, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Effect of barrier layer on the electrical and reliability characteristics of high-k gate dielectric films

K. Zawadzki, J.C. Lee, R. Nieh, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

A Study on Hysteresis Effect of Barium Strontium Titanate Thin Films for Alternative Gate Dielectric Application

Jack C. Lee, K. Zawadzki, B. Lee, 1999 .

90 nm generation, 300 mm wafer low k ILD/Cu interconnect technology

M. Bohr, A. Schmitz, R. Wu, 2003, Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695).

Effects of interfacial layer growth on the electrical characteristics of thin titanium oxide films on silicon

Yongjoo Jeon, Byoung Hun Lee, Keith Zawadzki, 1999 .