G. Ding

A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array

Mark Y. Liu, M. Bost, R. Brain, 2008, 2008 IEEE International Electron Devices Meeting.

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

R. Chau, C. Auth, M. Bost, 2007, 2007 IEEE International Electron Devices Meeting.

A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

C. Auth, V. Chikarmane, R. Heussner, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Design of near-Infrared reconfigurable metalens on Silicon-On-Insulator (SOI) platform with Fabry–Perrot phase shifter

Bayanheshig, G. Ding, Jinbo Gao, 2019, Optics Communications.

High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors

J. Jopling, J. Neirynck, H. Deshpande, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).