M. Iwai

High performance CMOSFET technology for 45nm generation

A. Oishi, T. Komoda, Y. Morimasa, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL

S. Takahashi, S. Yamada, S. Muramatsu, 2006, 2006 International Electron Devices Meeting.

Scalability of strained silicon CMOSFET and high drive current enhancement in the 40 nm gate length technology

A. Oishi, Y. Morimasa, T. Sanuki, 2003, IEEE International Electron Devices Meeting 2003.

High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique

K. Yahashi, A. Oishi, T. Komoda, 2006, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Variability aware modeling and characterization in standard cell in 45 nm CMOS with stress enhancement technique

T. Sanuki, M. Iwai, E. Morifuji, 2008, 2008 Symposium on VLSI Technology.

Layout Dependence Modeling for 45-nm CMOS With Stress-Enhanced Technique

M. Iwai, E. Morifuji, F. Matsuoka, 2009, IEEE Transactions on Electron Devices.