P. Hashemi

发表

Enhanced Hole Mobility in High Ge Content Asymmetrically Strained-SiGe p-MOSFETs

L. Gomez, C. Ni Chleirigh, P. Hashemi, 2010, IEEE Electron Device Letters.

Gate-all-around silicon nanowire MOSFETs : top-down fabrication and transport enhancement techniques

P. Hashemi, 2010 .

2-D modeling of potential distribution and threshold voltage of short channel fully depleted dual material gate SOI MESFET

Ali Afzali-Kusha, M. El Nokali, P. Hashemi, 2005 .

Two-dimensional analytical modeling and simulation of the potential and threshold voltage of a new fully depleted dual metal gate SOI MESFET

A. Behnam, P. Hashemi, A. Afzali-Kusha, 2004, Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004..

The influence of the stacked and double material gate structures on the short channel effects in SOI MOSFETs

A. Behnam, P. Hashemi, E. Fathi, 2004 .

Three-dimensional monolithic integration of III–V and Si(Ge) FETs for hybrid CMOS and beyond

Lukas Czornomaz, Karthik Balakrishnan, Thomas Morf, 2017 .

First RF characterization of InGaAs replacement metal gate (RMG) nFETs on SiGe-OI FinFETs fabricated by 3D monolithic integration

P. Hashemi, E. O'Connor, V. Djara, 2017, 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

Effect of germanium fraction on the effective minority carrier lifetime in thin film amorphous-Si/crystalline-Si1xGex/crystalline-Si heterojunction solar cells

P. Hashemi, J. Hoyt, S. Hadi, 2013 .

Record Hole Mobility at High Vertical Fields in Planar Strained Germanium on Insulator With Asymmetric Strain

D. Antoniadis, P. Hashemi, J. Hoyt, 2014, IEEE Electron Device Letters.

Key parameters affecting STT-MRAM switching efficiency and improved device performance of 400°C-compatible p-MTJs

D. Edelstein, C. Kothandaraman, P. Hashemi, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Demonstration of Nanosecond Operation in Stochastic Magnetic Tunnel Junctions.

P. Hashemi, P. Trouilloud, G. Hu, 2020, Nano letters.

Measurement and analysis of gate-induced drain leakage in short-channel strained silicon germanium-on-insulator pMOS FinFETs

P. Hashemi, J. Ott, E. Leobandung, 2014, 72nd Device Research Conference.

High performance and low leakage current InGaAs-on-silicon FinFETs with 20 nm gate length

M. Krishnan, E. Cartier, V. Narayanan, 2017, 2017 Symposium on VLSI Technology.

(Invited) Silicon Germanium FinFET Device Physics, Process Integration and Modeling Considerations

Pierre Morin, Ali Khakifirooz, Bruce B. Doris, 2014 .

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

T. Nagumo, N. Loubet, W. Schwarzenbach, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Fabrication of Strained-Si/Strained-Ge Heterostructures on Insulator

Judy L. Hoyt, Leonardo Gomez, Michael Canonico, 2008 .

Demonstration of Symmetric Lateral NPN Transistors on SOI Featuring Epitaxially Grown Emitter/Collector Regions

Kevin K. H. Chan, T. Ning, P. Hashemi, 2018, IEEE Journal of the Electron Devices Society.

High Performance InGaAs Gate-All-Around Nanosheet FET on Si Using Template Assisted Selective Epitaxy

G. Cohen, C. Lavoie, V. Narayanan, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Prospects of High-Ge-Content Strained SiGe for Advanced FinFET Generations

Kevin K. H. Chan, J. Bruley, P. Hashemi, 2016 .

Thin film a-Si/c-Si1−xGex/c-Si heterojunction solar cells with Ge content up to 56%

P. Hashemi, J. Hoyt, N. DiLello, 2012, 2012 38th IEEE Photovoltaic Specialists Conference.

Thin Film a-Si/c-Si1-xGex/c-Si Heterojunction Solar Cells: Design and Material Quality Requirements

P. Hashemi, J. Hoyt, S. Hadi, 2011, ECS Transactions.

Thin-film Si1−xGex HIT solar cells

P. Hashemi, J. Hoyt, S. Hadi, 2014 .

Effect of c-Si 1-x Ge x Thickness Grown by LPCVD on the Performance of Thin-Film a-Si/c-Si 1-x Ge x /c-Si Heterojunction Solar Cells

P. Hashemi, J. Hoyt, S. Hadi, 2012 .

a-Si/c-Si1−xGex/c-Si heterojunction solar cells

P. Hashemi, J. Hoyt, A. Nayfeh, 2011, 2011 International Conference on Simulation of Semiconductor Processes and Devices.

Prospects for Top-Down Fabricated Uniaxial Strained Nanowire MOSFETs

L. Gomez, P. Hashemi, J. Hoyt, 2008 .

Bias dependent conductance in CoFeB-MgO-CoFeB magnetic tunnel junctions as an indicator for electrode magnetic condition at barrier interfaces

P. Hashemi, P. Trouilloud, Jonathan Z. Sun, 2019, AIP Advances.

Gate-All-Around n-MOSFETs With Uniaxial Tensile Strain-Induced Performance Enhancement Scalable to Sub-10-nm Nanowire Diameter

P. Hashemi, L. Gomez, P. Hashemi, 2009, IEEE Electron Device Letters.

Electron transport in Gate-All-Around uniaxial tensile strained-Si nanowire n-MOSFETs

P. Hashemi, M. Canonico, L. Gomez, 2008, 2008 IEEE International Electron Devices Meeting.

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

D. Liu, P. Oldiges, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

Enhanced Hole Transport in Short-Channel Strained-SiGe p-MOSFETs

P. Hashemi, L. Gomez, P. Hashemi, 2009, IEEE Transactions on Electron Devices.

Toward High Performance SiGe Channel CMOS: Design of High Electron Mobility in SiGe nFinFETs Outperforming Si

V. Narayanan, H. Jagannathan, P. Hashemi, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

High Mobility High-Ge-Content SiGe PMOSFETs Using Al2O3/HfO2 Stacks With In-Situ O3 Treatment

Kevin K. H. Chan, E. Cartier, V. Narayanan, 2017, IEEE Electron Device Letters.

High Hole-Mobility Strained-$\hbox{Ge/Si}_{0.6} \hbox{Ge}_{0.4}$ P-MOSFETs With High-K/Metal Gate: Role of Strained-Si Cap Thickness

P. Hashemi, J. Hoyt, 2012, IEEE Electron Device Letters.

2X reduction of STT-MRAM switching current using double spin-torque magnetic tunnel junction

P. Hashemi, J. Nowak, P. Trouilloud, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET

M. Vinet, L. Grenouillet, T. Nagumo, 2012, 2012 International Electron Devices Meeting.

Detection of charge storage on molecular thin films of tris(8-hydroxyquinoline) aluminum (Alq3) by Kelvin force microscopy: a candidate system for high storage capacity memory cells.

Patrick R. Brown, V. Bulović, P. Hashemi, 2012, Nano letters.

Width-dependent hole mobility in top-down fabricated Si-core/Ge-shell nanowire metal-oxide-semiconductor-field-effect-transistors

Dimitri A. Antoniadis, Judy L. Hoyt, John Hennessy, 2010 .

Double spin-torque magnetic tunnel junction devices for last-level cache applications

J. Bruley, P. Hashemi, P. Trouilloud, 2022, 2022 International Electron Devices Meeting (IEDM).

Reliable Sub-Nanosecond Switching in Magnetic Tunnel Junctions for MRAM Applications

P. Hashemi, P. Trouilloud, G. Hu, 2022, IEEE Transactions on Electron Devices.

Spin-transfer torque MRAM with reliable 2 ns writing for last level cache applications

R. P. Robertazzi, N. Marchack, H. K. Lee, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Demonstration of narrow switching distributions in STTMRAM arrays for LLC applications at 1x nm node

P. Hashemi, J. Nowak, P. Trouilloud, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

High performance and reliable strained SiGe PMOS FinFETs enabled by advanced gate stack engineering

Eduard A. Cartier, Takashi Ando, Vijay Narayanan, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

High performance and record subthreshold swing demonstration in scaled RMG SiGe FinFETs with high-Ge-content channels formed by 3D condensation and a novel gate stack process

T. Ando, V. Narayanan, E. Leobandung, 2017, 2017 Symposium on VLSI Technology.

High performance PMOS with strained high-Ge-content SiGe fins for advanced logic applications

Kevin K. H. Chan, V. Narayanan, J. Bruley, 2017, 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Replacement high-K/metal-gate High-Ge-content strained SiGe FinFETs with high hole mobility and excellent SS and reliability at aggressive EOT ∼7Å and scaled dimensions down to sub-4nm fin widths

T. Ando, V. Narayanan, E. Leobandung, 2016, 2016 IEEE Symposium on VLSI Technology.

Asymmetric strain in nanoscale patterned strained-Si/strained-Ge/strained-Si heterostructures on insulator

L. Gomez, P. Hashemi, J. Hoyt, 2007 .

Fabrication and Characterization of Suspended Uniaxial Tensile Strained-Si Nanowires for Gate-All-Around Nanowire n-MOSFETs

Judy L. Hoyt, Karl K. Berggren, Leonardo Gomez, 2008, ECS Transactions.

Increased critical thickness for high Ge-content strained SiGe-on-Si using selective epitaxial growth

P. Hashemi, J. Hoyt, Meekyung Kim, 2010 .

First demonstration of high-Ge-content strained-Si1−xGex (x=0.5) on insulator PMOS FinFETs with high hole mobility and aggressively scaled fin dimensions and gate lengths for high-performance applications

Ali Khakifirooz, Karthik Balakrishnan, Sebastian U. Engelmann, 2014, 2014 IEEE International Electron Devices Meeting.

Strained Si1−xGex-on-insulator PMOS FinFETs with excellent sub-threshold leakage, extremely-high short-channel performance and source injection velocity for 10nm node and beyond

Kevin K. H. Chan, D. Antoniadis, P. Hashemi, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Reliable Five-Nanosecond Writing of Spin-Transfer Torque Magnetic Random-Access Memory

C. Kothandaraman, P. Hashemi, J. Nowak, 2019, IEEE Magnetics Letters.

Investigation of hole mobility in gate-all-around Si nanowire p-MOSFETs with high-к/metal-gate: Effects of hydrogen thermal annealing and nanowire shape

Judy L. Hoyt, James T. Teherani, Pouya Hashemi, 2010, 2010 International Electron Devices Meeting.