P. Moon

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

R. Chau, C. Auth, M. Bost, 2007, 2007 IEEE International Electron Devices Meeting.

A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects

M. Hussein, C. Kenyon, Z. Ma, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V

M. Hussein, C. Kenyon, E. Lee, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Correlation of plasma process induced charging with Fowler-Nordheim stress in p- and n-channel transistors

R. Chau, P. Moon, R. Chau, 1992, 1992 International Technical Digest on Electron Devices Meeting.

Process and Electrical Results for the On-die Interconnect Stack for Intel ’ s 45 nm Process Generation

Peter Moon, Kevin Fischer, V. Chikarmane, 2008 .

Process roadmap and challenges for metal barriers [copper interconnects]

K. Raol, P. Moon, P. Moon, 2003, IEEE International Electron Devices Meeting 2003.