M. Togo

发表

A salicide-bridged Trench capacitor with a Double-Sacrificial-Si3N4-Sidewall (DSS) for high-performance logic-embedded DRAMs : Special Issue on Advanced Memory Devices and Technologies

Takaho Tanigawa, H. Nobusawa, M. Togo, 1999 .

Impact of through silicon via induced mechanical stress on fully depleted Bulk FinFET technology

G. Beyer, E. Beyne, A. Thean, 2012, 2012 International Electron Devices Meeting.

Impact of single charged gate oxide defects on the performance and scaling of nanoscaled FETs

N. Horiguchi, L. Ragnarsson, T. Grasser, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

Variation improvement for manufacturable FINFET technology

Xing Zhang, Rohit Pal, Mitsuhiro Togo, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL

S. Takahashi, S. Yamada, S. Muramatsu, 2006, 2006 International Electron Devices Meeting.

A gate-side air-gap structure (GAS) to reduce the parasitic capacitance in MOSFETs

M. Togo, A. Tanabe, A. Furukawa, 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

High performance n-MOS finFET by damage-free, conformal extension doping

B. Douhard, N. Horiguchi, M. Togo, 2011, 2011 International Electron Devices Meeting.

Charge based compact model for bulk FinFETs

R. Ritzenthaler, M. Togo, C. Claeys, 2012, 2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS).

Simple current and capacitance methods for bulk finFET height extraction and correlation to device variability

N. Horiguchi, B. Parvais, T. Hoffmann, 2011, 2011 IEEE ICMTS International Conference on Microelectronic Test Structures.

Time-Dependent Dielectric Breakdown on Subnanometer EOT nMOS FinFETs

M. Togo, G. Groeseneken, T. Kauerauf, 2012, IEEE Transactions on Device and Materials Reliability.

Controlling the Concentration and Position of Nitrogen in Ultrathin Oxynitride Films Formed by Using Oxygen and Nitrogen Radicals

T. Tatsumi, M. Togo, Koji Watanabe, 1999 .

Low-Leakage and Highly Reliable 1.5 nm SiON Gate Dielectric Using Radical Oxynitridation for Sub-0.1 μm CMOS

M. Togo, T. Mogami, Koji Watanabe, 2001 .

Reliability in gate first and gate last ultra-thin-EOT gate stacks assessed with CV-eMSM BTI characterization

S. Chew, T. Schram, A. Veloso, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Superior NBTI reliability of SiGe channel pMOSFETs: Replacement gate, FinFETs, and impact of Body Bias

A. Hikavyy, N. Horiguchi, L. Ragnarsson, 2011, 2011 International Electron Devices Meeting.

1/f noise analysis of replacement metal gate bulk p-type fin field effect transistor

R. Ritzenthaler, N. Horiguchi, A. Thean, 2013 .

Effects of gate process on NBTI characteristics of TiN gate FinFET

N. Horiguchi, M. Togo, B. Lee, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

Dependence of electrical properties on nitrogen profile in ultrathin oxynitride gate dielectrics formed by using oxygen and nitrogen radicals

T. Tatsumi, M. Togo, T. Mogami, 2001 .

Improving the quality of sub-1.5-nm-thick oxynitride gate dielectric for FETs with narrow channel and shallow-trench isolation using radical oxygen and nitrogen

M. Terai, T. Tatsumi, M. Togo, 2002 .

Improved sidewall doping of extensions by AsH3 ion assisted deposition and doping (IADD) with small implant angle for scaled NMOS Si bulk FinFETs

K. B. Noh, M. Kim, S. Chew, 2013, 2013 IEEE International Electron Devices Meeting.

Negative Bias Temperature Instability in p-FinFETs With 45 $^{\circ}$ Substrate Rotation

R. Ritzenthaler, N. Horiguchi, B. Kaczer, 2013, IEEE Electron Device Letters.

Atom Probe Tomography for 3D-dopant analysis in FinFET devices

N. Horiguchi, M. Togo, W. Vandervorst, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Recoiled-oxygen-free processing for 1.5 nm SiON gate-dielectric in sub-100-nm CMOS technology

M. Togo, T. Mogami, S. Kimura, 2002 .

Repair of Electromigration-Induced Voids in Aluminum Interconnection by Current Reversal

M. Togo, K. Hoh, Chao-Fu Hong, 1993 .

Stress Techniques and Mobility Enhancement in FinFET Architectures

Naoto Horiguchi, Geert Hellings, Anabela Veloso, 2013 .

Ultrathin EOT high-κ/metal gate devices for future technologies: Challenges, achievements and perspectives (invited)

Tom Schram, T. Chiarella, M. Togo, 2011 .

Effects of Selecting Channel Direction in Improving Performance of Sub-100 nm MOSFETs Fabricated on (110) Surface Si Substrate

Masami Hane, T. Iwamoto, Tatsuya Ezaki, 2004 .

A robust 65-nm node CMOS technology for wide-range Vdd operation

T. Fukai, T. Tamura, M. Togo, 2003, IEEE International Electron Devices Meeting 2003.

Phosphorus doped SiC Source Drain and SiGe channel for scaled bulk FinFETs

R. Ritzenthaler, A. Hikavyy, G. Mannaert, 2012, 2012 International Electron Devices Meeting.

Process-Dependent N/PBTI Characteristics of TiN Gate FinFETs

Byoung Hun Lee, L. Pantisano, T. Chiarella, 2012, IEEE Electron Device Letters.

Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements

Massimo Alioto, Naoto Horiguchi, Guido Groeseneken, 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

Power-aware 65 nm node CMOS technology using variable V/sub DD/ and back-bias control with reliability consideration for back-bias mode

T. Fukai, M. Togo, K. Imai, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Heated implantation with amorphous Carbon CMOS mask for scaled FinFETs

R. Ritzenthaler, G. Mannaert, H. Dekkers, 2013, 2013 Symposium on VLSI Technology.