S. Narayanan

Implementation of a third-generation 1.1-GHz 64-bit microprocessor

Alan Smith, Sung-Hun Oh, S. Narayanan, 2002, IEEE J. Solid State Circuits.

Configuring multiple scan chains for minimum test time

R. Gupta, Rajesh K. Gupta, S. Narayanan, 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

Optimal Configuring of Multiple

Sridhar Narayanan, Rajesh Gupta, Melvin A. Scan Chains, 1993 .

IODINE: a tool to automatically infer dynamic invariants for hardware designs

Sridhar Narayanan, Sandeep Chakravorty, Sudheendra Hangal, 2005, Proceedings. 42nd Design Automation Conference, 2005..

An efficient scheme to diagnose scan chains

S. Narayanan, A. Das, S. Narayanan, 1997, Proceedings International Test Conference 1997.

Optimal Configuring of Multiple Scan Chains

Melvin A. Breuer, Sridhar Narayanan, Rajesh Gupta, 1993, IEEE Trans. Computers.

Reconfigurable scan chains: A novel approach to reduce test application time

Melvin A. Breuer, Sridhar Narayanan, S. Narayanan, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

Asynchronous multiple scan chains

Melvin A. Breuer, Sridhar Narayanan, S. Narayanan, 1995, Proceedings 13th IEEE VLSI Test Symposium.

TSOtool: a program for verifying memory systems using the memory consistency model

Sridhar Narayanan, Sudheendra Hangal, Durgam Vahia, 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..