H. Takato

A fully planarized 0.25 /spl mu/m CMOS technology for 256 Mbit DRAM and beyond

R. Kleinhenz, T. Mii, H. Aochi, 1995, 1995 Symposium on VLSI Technology. Digest of Technical Papers.

A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs

S. Inoue, F. Masuoka, A. Nitayama, 1989, International Technical Digest on Electron Devices Meeting.

A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's

Fumio Horiguchi, Yukihito Oowaki, Shigeyoshi Watanabe, 1995 .

Impact of surrounding gate transistor (SGT) for ultra-high-density LSI's

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1991 .

Multi-pillar surrounding gate transistor (M-SGT) for compact and high-speed circuits

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1991 .

High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs

Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, 1988, Technical Digest., International Electron Devices Meeting.

A sub-10-ns 16/spl times/16 multiplier using 0.6-/spl mu/m CMOS technology

Yukihito Oowaki, Shigeyoshi Watanabe, Akihiro Nitayama, 1987 .

Double LDD concave (DLC) structure for sub-half micron MOSFET

F. Masuoka, A. Nitayama, K. Sunouchi, 1988, Technical Digest., International Electron Devices Meeting.