Greg M. Link

发表

Evaluating alternative implementations for LDPC decoder check node function

Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides, 2004, IEEE Computer Society Annual Symposium on VLSI.

A holistic approach to designing energy-efficient cluster interconnects

Mahmut T. Kandemir, Chita R. Das, Narayanan Vijaykrishnan, 2005, IEEE Transactions on Computers.

Embedded hardware face detection

Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides, 2004, 17th International Conference on VLSI Design. Proceedings..

Interconnect and thermal-aware floorplanning for 3D microprocessors

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection

Mahmut T. Kandemir, Yuan Xie, Robert P. Dick, 2005, ASP-DAC.

Temperature-aware voltage islands architecting in system-on-chip design

Narayanan Vijaykrishnan, Yuan Xie, Nagu R. Dhanwada, 2005, 2005 International Conference on Computer Design.

Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers

Narayanan Vijaykrishnan, Yehia Massoud, Greg M. Link, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip

Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides, 2005, Adv. Comput..

Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers

Narayanan Vijaykrishnan, Yehia Massoud, Greg M. Link, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

Implementing LDPC decoding on network-on-chip

Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Thermally Robust Clocking Schemes for 3D Integrated Circuits

Narayanan Vijaykrishnan, Yehia Massoud, Greg M. Link, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Fault tolerant algorithms for network-on-chip interconnect

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, IEEE Computer Society Annual Symposium on VLSI.

Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures

Shuai Wang, Jie S. Hu, Sotirios G. Ziavras, 2005, Asia-Pacific Computer Systems Architecture Conference.

Load Miss Prediction - Exploiting Power Performance Trade-offs

Mary Jane Irwin, Padma Raghavan, Konrad Malkowski, 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

A generic reconfigurable neural network architecture as a network on chip

Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides, 2004, IEEE International SOC Conference, 2004. Proceedings..

Energy optimization techniques in cluster interconnects

Mahmut T. Kandemir, Chita R. Das, Narayanan Vijaykrishnan, 2003, ISLPED '03.

Hotspot prevention through runtime reconfiguration in network-on-chip

Narayanan Vijaykrishnan, Greg M. Link, 2005, Design, Automation and Test in Europe.

Thermal trends in emerging technologies

Narayanan Vijaykrishnan, Greg M. Link, N. Vijaykrishnan, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Energy/performance modeling for collective communication in 3-D torus cluster networks

Mary Jane Irwin, Padma Raghavan, Greg M. Link, 2006, SC.