G. Taylor

Security Evaluation of Asynchronous Circuits

George S. Taylor, Simon W. Moore, Huiyun Li, 2003, CHES.

An in-cache address translation mechanism

Randy H. Katz, David A. Wood, George S. Taylor, 1986, ISCA '86.

Design Decisions in SPUR

James R. Larus, Randy H. Katz, David A. Wood, 1986, Computer.

An in-cache address translation mechanism

David A. Wood, Mark D. Hill, Susan J. Eggers, 1986, ISCA '86.

Point to point GALS interconnect

Peter Robinson, George S. Taylor, Simon W. Moore, 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

Improving smart card security using self-timed circuits

George S. Taylor, Ross J. Anderson, Simon W. Moore, 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

Self calibrating clocks for globally asynchronous locally synchronous systems

Peter Robinson, George S. Taylor, Simon W. Moore, 2000, Proceedings 2000 International Conference on Computer Design.

An on-chip dynamically recalibrated delay line for embedded self-timed systems

Peter Robinson, George S. Taylor, Simon W. Moore, 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

Evaluation of the SPUR Lisp architecture

James R. Larus, George S. Taylor, David A. Patterson, 1986, ISCA '86.

The TLB slice-a low-cost high-speed address translation mechanism

Peter Davies, George Taylor, Michael Farmwald, 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.

SPUR: A VLSI Multiprocessor Workstation

James R. Larus, Randy H. Katz, David A. Wood, 1985 .