Xrysovalantis Kavousianos

发表

Generation of compact test sets with high defect coverage

Krishnendu Chakrabarty, Xrysovalantis Kavousianos, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

On the design of self-testing checkers for modified Berger codes

Stanislaw J. Piestrak, Dimitris Bakalis, Xrysovalantis Kavousianos, 2001, Proceedings Seventh International On-Line Testing Workshop.

Time-division multiplexing for testing SoCs with DVS and multiple voltage islands

Krishnendu Chakrabarty, Rubin A. Parekhji, Arvind Jain, 2012, 2012 17th IEEE European Test Symposium (ETS).

Test-access-mechanism optimization for multi-Vdd SoCs

Krishnendu Chakrabarty, Panagiotis Georgiou, Xrysovalantis Kavousianos, 2015, 2015 IEEE International Test Conference (ITC).

A new built-in TPG method for circuits with random patternresistant faults

Spyros Tragoudas, Dimitris Nikolos, Dimitris Bakalis, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands

Krishnendu Chakrabarty, Rubin A. Parekhji, Arvind Jain, 2011, 2011 Asian Test Symposium.

A branch-&-bound algorithm for TAM optimization in multi-Vdd SoCs

Krishnendu Chakrabarty, Xrysovalantis Kavousianos, Fotios Vartziotis, 2015, 2015 20th IEEE European Test Symposium (ETS).

Novel single and double output TSC Berger code checkers

Dimitris Nikolos, Xrysovalantis Kavousianos, 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

Timing Error Detection and Correction by Time Dilation

Yiorgos Tsiatouhas, Andreas Floros, Xrysovalantis Kavousianos, 2008, VLSI-SoC.

Efficient Test-Data Compression for IP Cores Using Multilevel Huffman Coding

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

New efficient totally self-checking Berger code checkers

Dimitris Nikolos, Xrysovalantis Kavousianos, G. Foukarakis, 1999, Integr..

Reseeding-based test set embedding with reduced test sequences

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2005, Sixth international symposium on quality electronic design (isqed'05).

Built-In Self-Test, Diagnosis, and Repair of MultiMode Power Switches

Krishnendu Chakrabarty, Yiorgos Tsiatouhas, Zhaobo Zhang, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

The Time Dilation Technique for Timing Error Tolerance

Yiorgos Tsiatouhas, Angela Arapoyanni, Andreas Floros, 2014, IEEE Transactions on Computers.

Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing

Krishnendu Chakrabarty, Rubin A. Parekhji, Arvind Jain, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Modular TSC checkers for Bose-Lin and Bose codes

Dimitris Nikolos, Xrysovalantis Kavousianos, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

On accumulator-based bit-serial test response compaction schemes

Haridimos T. Vergos, Dimitris Nikolos, Dimitris Bakalis, 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

Testing for SoCs with advanced static and dynamic power-management capabilities

Krishnendu Chakrabarty, Xrysovalantis Kavousianos, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Efficient partial scan cell gating for low-power scan-based testing

Dimitris Nikolos, Dimitris Bakalis, Xrysovalantis Kavousianos, 2009, TODE.

Self-Freeze Linear Decompressors: Test Pattern Generators for Low Power Scan Testing

Xrysovalantis Kavousianos, Vasileios Tenentes, 2010, ISVLSI.

On-chip deterministic counter-based TPG with low heat dissipation

Spyros Tragoudas, Dimitris Nikolos, Xrysovalantis Kavousianos, 1999, 1999 Southwest Symposium on Mixed-Signal Design (Cat. No.99EX286).

State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores

Emmanouil Kalligeros, Xrysovalantis Kavousianos, Vasileios Tenentes, 2008, 2008 Design, Automation and Test in Europe.

A Robust and Reconfigurable Multi-mode Power Gating Architecture

Krishnendu Chakrabarty, Yiorgos Tsiatouhas, Zhaobo Zhang, 2011, 2011 24th Internatioal Conference on VLSI Design.

Critical path — Oriented & thermal aware X-filling for high un-modeled defect coverage

Xrysovalantis Kavousianos, Fotis Vartziotis, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

New reseeding technique for LFSR-based test pattern generation

Emmanouil Kalligeros, Dimitris Nikolos, Dimitris Bakalis, 2001, Proceedings Seventh International On-Line Testing Workshop.

On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST

Emmanouil Kalligeros, Dimitris Nikolos, Dimitris Bakalis, 2002, J. Electron. Test..

Generation of Compact Stuck-At Test Sets Targeting Unmodeled Defects

Krishnendu Chakrabarty, Xrysovalantis Kavousianos, K. Chakrabarty, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Two-dimensional time-division multiplexing for 3D-SoCs

Krishnendu Chakrabarty, Xrysovalantis Kavousianos, Fotios Vartziotis, 2016, 2016 21th IEEE European Test Symposium (ETS).

Multiphase BIST: a new reseeding technique for high test-data compression

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Time-Division Multiplexing for Testing DVFS-Based SoCs

Krishnendu Chakrabarty, Rubin A. Parekhji, Arvind Jain, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Placement and Routing in Computer Aided Design of Standard Cell Arrays by Exploiting the Structure of the Interconnection Graph

Yiorgos Tsiatouhas, Ioannis Fudos, Dimitrios Markouzis, 2008 .

Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands

Krishnendu Chakrabarty, Rubin A. Parekhji, Arvind Jain, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Self-Freeze Linear Decompressors for Low Power Testing

Xrysovalantis Kavousianos, Vasileios Tenentes, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

LFSR-based test-data compression with self-stoppable seeds

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-at Test Sets

Emmanouil Kalligeros, Krishnendu Chakrabarty, Xrysovalantis Kavousianos, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches

Krishnendu Chakrabarty, Yiorgos Tsiatouhas, Yan Luo, 2011, 2011 Sixteenth IEEE European Test Symposium.

Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches

Krishnendu Chakrabarty, Yiorgos Tsiatouhas, Zhaobo Zhang, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

K3 TAM Optimization for Testing 3D-SoCs using Non-Regular Time-Division-Multiplexing

Panagiotis Georgiou, Xrysovalantis Kavousianos, Iakovos Theodosopoulos, 2019, 2019 IEEE European Test Symposium (ETS).

Reprints Available Directly from the Publisher Photocopying Permitted by License Only (c) 2001 Opa (overseas Publishers Association) N.v. Low Power Built-in Self-test Schemes for Array and Booth Multipliers*

Haridimos T. Vergos, George Alexiou, Dimitris Nikolos, 2022 .

A BIST scheme for testing and repair of multi-mode power switches

Krishnendu Chakrabarty, Yiorgos Tsiatouhas, Zhaobo Zhang, 2011, 2011 IEEE 17th International On-Line Testing Symposium.

Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An efficient test vector ordering method for low power testing

Dimitris Nikolos, Dimitris Bakalis, Xrysovalantis Kavousianos, 2004, IEEE Computer Society Annual Symposium on VLSI.

Fault-Independent Test-Generation for Software-Based Self-Testing

Riccardo Cantoro, Panagiotis Georgiou, Xrysovalantis Kavousianos, 2018 .

DV-TSE: Difference Vector Based Test Set Embedding

Dimitris Nikolos, Dimitrios Kagaris, Xrysovalantis Kavousianos, 2003, VLSI-SOC.

High-Quality Statistical Test Compression With Narrow ATE Interface

Xrysovalantis Kavousianos, Vasileios Tenentes, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs

Xrysovalantis Kavousianos, Vasileios Tenentes, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A highly regular multi-phase reseeding technique for scan-based BIST

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2003, GLSVLSI '03.

Recent advances in single- and multi-site test optimization for DVS-based SoCs

Krishnendu Chakrabarty, Xrysovalantis Kavousianos, K. Chakrabarty, 2014, 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

A ROMless LFSR reseeding scheme for scan-based BIST

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Virtual-scan: a novel approach for software-based self-testing of microprocessors

Giorgos Dimitrakopoulos, Dimitris Nikolos, Xrysovalantis Kavousianos, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

2015 JETTA Reviewers

Robert Wille, Yong-Bin Kim, Alexandre M. Amory, 2016, Journal of electronic testing.

Low power dissipation in BIST schemes for modified Booth multipliers

Haridimos T. Vergos, George Alexiou, Dimitris Nikolos, 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

Optimal Selective Huffman Coding for Test-Data Compression

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2007, IEEE Transactions on Computers.

Efficient multiphase test set embedding for scan-based testing

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Testing 3D-SoCs Using 2-D Time-Division Multiplexing

Krishnendu Chakrabarty, Panagiotis Georgiou, Xrysovalantis Kavousianos, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Fault-Independent Test-Generation for Software-Based Self-Testing

Matteo Sonza Reorda, Riccardo Cantoro, Panagiotis Georgiou, 2018, 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).

Power aware test-data compression for scan-based testing

Emmanouil Kalligeros, Dimitris Nikolos, Xrysovalantis Kavousianos, 2005, 2005 12th IEEE International Conference on Electronics, Circuits and Systems.

Novel Single and Double Output TSC CMOS Checkers for m-out-of-n Codes

Dimitris Nikolos, Xrysovalantis Kavousianos, G. Sidiropoulos, 2000, VLSI Design.

Defect Coverage-Driven Window-Based Test Compression

Emmanouil Kalligeros, Krishnendu Chakrabarty, Xrysovalantis Kavousianos, 2010, 2010 19th IEEE Asian Test Symposium.

Single and Variable-State-Skip LFSRs: Bridging the Gap Between Test Data Compression and Test Set Embedding for IP Cores

Emmanouil Kalligeros, Xrysovalantis Kavousianos, Vasileios Tenentes, 2010, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register

Dimitris Nikolos, Dimitris Bakalis, Xrysovalantis Kavousianos, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

A novel reseeding technique for accumulator-based test pattern generation

Dimitris Nikolos, Dimitris Bakalis, Xrysovalantis Kavousianos, 2001, GLSVLSI '01.

A Branch-&-Bound Test-Access-Mechanism Optimization Method for Multi- $V_{\mathrm{ dd}}$ SoCs

Krishnendu Chakrabarty, Panagiotis Georgiou, Xrysovalantis Kavousianos, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An efficient seeds selection method for LFSR-based test-per-clock BIST

Emmanouil Kalligeros, Dimitris Nikolos, Dimitris Bakalis, 2002, Proceedings International Symposium on Quality Electronic Design.

Defect aware X-filling for low-power scan testing

Krishnendu Chakrabarty, Xrysovalantis Kavousianos, Vasileios Tenentes, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Self-exercising self testing k-order comparators

Dimitris Nikolos, Xrysovalantis Kavousianos, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

Low power testing by test vector ordering with vector repetition

Dimitris Nikolos, Dimitris Bakalis, Xrysovalantis Kavousianos, 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

Design of compact and high speed totally self-checking CMOS checkers for m-out-of-n codes

Dimitris Nikolos, Xrysovalantis Kavousianos, G. Sidiropoulos, 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

1 Generation of Compact Single-Detect Stuck-At Test Sets Targeting Unmodeled Defects

Krishnendu Chakrabarty, Xrysovalantis Kavousianos, 2010 .

Low Power Test-Compression for High Test-Quality and Low Test-Data Volume

Xrysovalantis Kavousianos, Vasileios Tenentes, 2011, 2011 Asian Test Symposium.