D. Anand

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining

J.E. Barth, D. Anand, S. Burns, 2004, IEEE Journal of Solid-State Circuits.

A 5.6 ns random cycle 144 Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface

J. Barth, D. Anand, S. Burns, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

Turning Logic Transistors into Secure, Multi-Time Programmable, Embedded Non-Volatile Memory Elements for 14 nm FINFET Technologies and Beyond

R. Katz, F. Khan, D. Moy, 2019, 2019 Symposium on VLSI Technology.

Generating At-Speed array fail maps with low-speed ATE

Darren Anand, Kevin W. Gorman, Michael R. Nelms, 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..