J. Dreibelbis

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining

J.E. Barth, D. Anand, S. Burns, 2004, IEEE Journal of Solid-State Circuits.

Processor-based built-in self-test for embedded DRAM

Howard Leo Kalter, John E. Barth, Jeffrey H. Dreibelbis, 1998, IEEE J. Solid State Circuits.

An ASIC library granular DRAM macro with built-in self test

R. Kho, J. Dreibelbis, J. Barth, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).