J. Fifield

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining

J.E. Barth, D. Anand, S. Burns, 2004, IEEE Journal of Solid-State Circuits.

Scaled-up commercial production of reactive magnesia cement pressed masonry units. Part II: Performance of the commercial blocks

Abir Al-Tabbaa, M. Liska, John Fifield, 2012 .

Scaled-up commercial production of reactive magnesium cement pressed masonry units. Part I: Production

Abir Al-Tabbaa, John Fifield, M. Liska, 2012 .

A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC

Howard Leo Kalter, C. H. Stapper, John E. Barth, 1990 .

A 50 ns 16 Mb DRAM with a 10 ns data rate

J. Dilorenzo, H. Kalter, C. Stapper, 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

Reliability and design qualification of a sub-micron tungsten silicide E-Fuse

J.A. Fifield, W.R. Tonti, J. Higgins, 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.