S. Haendler

发表

FDSOI devices with thin BOX and ground plane integration for 32nm node and below

E. Deloffre, O. Faynot, T. Skotnicki, 2008 .

28nm FDSOI technology platform for high-speed low-voltage digital applications

O. Rozeau, D. Noblet, M. Rafik, 2012, 2012 Symposium on VLSI Technology (VLSIT).

SOI Technologies Overview for Low-Power Low-Voltage Radio-Frequency Applications

O. Rozeau, Sebastien Haendler, J. Boussey, 2000 .

A 55 nm triple gate oxide 9 metal layers SiGe BiCMOS technology featuring 320 GHz fT / 370 GHz fMAX HBT and high-Q millimeter-wave passives

P. Chevalier, Y. Campidelli, D. Gloria, 2014, 2014 IEEE International Electron Devices Meeting.

Silicon characterization of standby leakage reduction techniques in a 0.13μm Low Power Partially-Depleted Silicon-On-Insulator Technology

M. Belleville, S. Haendler, P. Flatresse, 2006, 2006 IEEE International Conference on IC Design and Technology.

Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

G. Ghibaudo, S. Haendler, N. Planes, 2015, IEEE Transactions on Electron Devices.

Development of Analytical Compact Drain Current Model For 28 nm FDSOI MOSFETs U

S. Haendler, 2015 .

Low frequency noise and hot-carrier reliability in advanced SOI MOSFETs

S. Haendler, Jalal Jomaah, Francis Balestra, 2004 .

Enhancement of devices performance of hybrid FDSOI/bulk technology by using UTBOX sSOI substrates

O. Faynot, F. Andrieu, N. Planes, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Low frequency noise in 0.12 mum partially and fully depleted SOI technology

Sébastien Haendler, Francis Balestra, Jalal Jomaah, 2003, Microelectron. Reliab..

Improved analysis and modeling of low-frequency noise in nanoscale MOSFETs

J. Jomaah, G. Ghibaudo, S. Haendler, 2012 .

Low frequency noise variability in ultra scaled FD-SOI n-MOSFETs: Dependence on gate bias, frequency and temperature

G. Ghibaudo, S. Haendler, E. Josse, 2016 .

Measurement and characterization of low frequency noise collector current in 0.13 μm SiGe:C HBTs

P. Chevalier, D. Gloria, S. Haendler, 2015, International Conference on Noise and Fluctuations.

Study of Hot-Carrier-Induced Traps in Nanoscale UTBB FD-SOI MOSFETs by Low-Frequency Noise Measurements

G. Ghibaudo, S. Haendler, N. Planes, 2016, IEEE Transactions on Electron Devices.

Optimizing the salicide thickness for improving 130 nm PD SOI performances

S. Haendler, R. Gwoziecki, C. Tabone, 2003, 2003 IEEE International Conference on SOI.

Shrinking from 0.25 µm down to 0.12 µm SOI CMOS technology node: a contribution to 1/f noise in partially depleted n-MOSFETs

Christina De Meyer, C. Raynaud, Jalal Jomaah, 2002 .

Characterization and Modeling of NBTI in Nanoscale UltraThin Body UltraThin Box FD-SOI MOSFETs

G. Ghibaudo, S. Haendler, N. Planes, 2016, IEEE Transactions on Electron Devices.

Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below

O. Faynot, F. Andrieu, T. Skotnicki, 2010, 2009 Proceedings of ESSCIRC.

FDSOI devices with thin BOX and ground plane integration for 32nm node and below

X. Garros, O. Faynot, C. Laviron, 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

FDSOI process/design full solutions for ultra low leakage, high speed and low voltage SRAMs

R. Ranica, D. Noblet, N. Planes, 2013, 2013 Symposium on VLSI Technology.

Drain current local variability from linear to saturation region in 28nm bulk NMOSFETs

G. Ghibaudo, S. Haendler, T. A. Karatsori, 2017, 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

Reliability assessment of 4GSP/s interleaved SAR ADC

Sylvain Bourdel, Sébastien Haendler, Ph. Benech, 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology

Sébastien Haendler, Hassen Aziza, Alexandre Malherbe, 2021, 2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Hot-carrier degradation model for nanoscale ultra-thin body ultra-thin box SOI MOSFETs suitable for circuit simulators

G. Ghibaudo, S. Haendler, N. Planes, 2016 .

Efficient multi-VT FDSOI technology with UTBOX for low power circuit design

O. Faynot, F. Andrieu, T. Skotnicki, 2010, 2010 Symposium on VLSI Technology.

Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology

X. Garros, O. Faynot, D. Noblet, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below

T. Skotnicki, Sébastien Haendler, F. Leverd, 2009, 2009 Proceedings of the European Solid State Device Research Conference.

Full gate voltage range Lambert-function based methodology for FDSOI MOSFET parameter extraction

Sebastien Haendler, T. A. Karatsori, Charalabos A. Dimitriadis, 2015 .

Universality of trap-induced mobility fluctuations between 1/f noise and random telegraph noise in nanoscale FD-SOI MOSFETs

S. Haendler, Q. Rafhay, C. Theodorou, 2023, Applied Physics Letters.

Static and LFN/RTN Local and Global Variability Analysis Using an Addressable Array Test Structure

S. Haendler, Q. Rafhay, C. Theodorou, 2023, 2023 35th International Conference on Microelectronic Test Structure (ICMTS).

New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs

Sébastien Haendler, Gérard Ghibaudo, Nicolas Planes, 2015, 2015 IEEE International Reliability Physics Symposium.

Drain-Current Flicker Noise Modeling in nMOSFETs From a 14-nm FDSOI Technology

Gerard Ghibaudo, Sebastien Haendler, Eleftherios G. Ioannidis, 2015, IEEE Transactions on Electron Devices.

Evolution of low frequency noise and noise variability through CMOS bulk technology nodes

G. Ghibaudo, J. Rosa, S. Haendler, 2013, 2013 22nd International Conference on Noise and Fluctuations (ICNF).

Characterization and modeling of low frequency noise in CMOS inverters

Sebastien Haendler, Charalabos A. Dimitriadis, Gerard Ghibaudo, 2013 .

Low frequency noise variability in high-k/metal gate stack 28nm bulk and FD-SOI CMOS transistors

G. Ghibaudo, N. Planes, M. Haond, 2011, 2011 International Electron Devices Meeting.

Low-Frequency Noise Investigation and Noise Variability Analysis in High- $k$/Metal Gate 32-nm CMOS Transistors

G. Ghibaudo, G. Bidal, S. Haendler, 2011, IEEE Transactions on Electron Devices.

Self-Heating Effect in FDSOI Transistors Down to Cryogenic Operation at 4.2 K

G. Ghibaudo, M. Vinet, S. Haendler, 2019, IEEE Transactions on Electron Devices.

Enhanced design performance thanks to adaptative body biasing technique in FDSOI technolologies

F. Arnaud, P. Flatresse, S. Haendler, 2017, 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

4th INTERNATIONAL CONFERENCE ON MODERN CIRCUITS AND SYSTEMS TECHNOLOGIES

Orso, O. Weber, F. Andrieu, 2015 .

ON THE 1/F NOISE IN FULLY DEPLETED SOI TRANSISTORS

S. Haendler, Jalal Jomaah, F. Dieudonne, 2001 .

Comparative low frequency noise analysis in various SOI devices: floating body, body-tied, DTMOS with and without current limiter

S. Haendler, J. L. Pelloie, Jalal Jomaah, 2000, 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125).

Sebastien Haendler, Jalal Jomaah, Christine Raynaud, 2000 .

Low Frequency Noise in advanced 55nm BiCMOS SiGeC Heterojunction Bipolar Transistors: Impact of collector doping

P. Chevalier, D. Gloria, S. Haendler, 2017, 2017 International Conference on Noise and Fluctuations (ICNF).

Low frequency noise measurements of advanced BiCMOS SiGeC Heterojunction Bipolar Transistors used for mm-Wave to terahertz applications

P. Chevalier, D. Gloria, S. Haendler, 2013, 2013 22nd International Conference on Noise and Fluctuations (ICNF).

Improvement of 1/f noise in advanced 0.13 µm BiCMOS SiGe:C Heterojunction Bipolar Transistors

S. Haendler, G. Morin, A. Hoffmann, 2011, 2011 21st International Conference on Noise and Fluctuations.

Variability Evaluation of 28nm FD-SOI Technology at Cryogenic Temperatures down to 100mK for Quantum Computing

G. Ghibaudo, M. Cassé, S. Haendler, 2020, 2020 IEEE Symposium on VLSI Technology.

Front and back channels coupling and transport on 28 nm FD-SOI MOSFETs down to liquid-He temperature

G. Ghibaudo, M. Cassé, S. Haendler, 2021 .

Electrostatics and channel coupling on 28 nm FD-SOIfor cryogenic applications

G. Ghibaudo, M. Cassé, S. Haendler, 2020, 2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

Integrated Variability Measurements of 28 nm FDSOI MOSFETs down to 4.2 K for Cryogenic CMOS Applications

G. Ghibaudo, M. Cassé, S. Haendler, 2020, 2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS).

Impact of Source–Drain Series Resistance on Drain Current Mismatch in Advanced Fully Depleted SOI n-MOSFETs

G. Ghibaudo, S. Haendler, E. Josse, 2015, IEEE Electron Device Letters.

Shrinking from 0.25 down to 0.12 μm SOI CMOS technology node: a contribution to low-frequency noise in partially depleted N-MOSFETs

F. Balestra, Jalal Jomaah, S. Haendler, 2003 .

Improved analysis of low frequency noise in dynamic threshold MOS/SOI transistors

Sébastien Haendler, Gérard Ghibaudo, Jalal Jomaah, 2001, Microelectron. Reliab..