F. Leverd

发表

FDSOI devices with thin BOX and ground plane integration for 32nm node and below

E. Deloffre, O. Faynot, T. Skotnicki, 2008 .

A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications

G. Masini, D. Gloria, R. Beneyton, 2013, 2013 IEEE International Electron Devices Meeting.

50 nm-Gate All Around (GAA)-Silicon On Nothing (SON)-devices: a simple way to co-integration of GAA transistors within bulk MOSFET process

T. Skotnicki, D. Dutartre, P. Ribot, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Fully-depleted SOI CMOS technology using WXN metal gate and HfSixOyNZ high-k dielectric

O. Faynot, M. Orlowski, T. Skotnicki, 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

A Silicon Photonics Technology for 400 Gbit/s Applications

S. Monfray, F. Leverd, N. Vulliet, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

A 55 nm triple gate oxide 9 metal layers SiGe BiCMOS technology featuring 320 GHz fT / 370 GHz fMAX HBT and high-Q millimeter-wave passives

P. Chevalier, Y. Campidelli, D. Gloria, 2014, 2014 IEEE International Electron Devices Meeting.

Stress Memorization Technique (SMT) Optimization for 45nm CMOS

P. Stolk, F. Leverd, F. Arnaud, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Totally silicided (CoSi/sub 2/) polysilicon: a novel approach to very low-resistive gate (/spl sim/2/spl Omega///spl square/) without metal CMP nor etching

T. Skotnicki, F. Leverd, B. Tavel, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

A 150GHz f/sub T//f/sub max/ 0.13/spl mu/m SiGe:C BiCMOS technology

F. Leverd, R. Beerkens, M. Laurens, 2003, 2003 Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (IEEE Cat. No.03CH37440).

Holed MEM resonators with high aspect ratio, for high accuracy frequency trimming

F. Leverd, J. Carpentier, D. Mercier, 2011, 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

Ultra-Thin (4nm) Gate-All-Around CMOS devices with High-k/Metal for Low Power Multimedia Applications

Nicolas Loubet, Stephane Monfray, G. Bidal, 2010 .

Gate-All-Around technology: taking advantage of ballistic transport ?

G. Ghibaudo, T. Skotnicki, S. Monfray, 2009, ESSDERC 2009.

Patterning of silicon nitride for CMOS gate spacer technology. II. Impact of subsilicon surface carbon implantation on epitaxial regrowth

F. Leverd, R. Blanc, C. Jenny, 2014 .

Patterning of silicon nitride for CMOS gate spacer technology. I. Mechanisms involved in the silicon consumption in CH3F/O2/He high density plasmas

F. Leverd, R. Blanc, O. Joubert, 2013 .

Hybrid Localized SOI/bulk technology for low power system-on-chip

O. Faynot, G. Ghibaudo, T. Skotnicki, 2010, 2010 Symposium on VLSI Technology.

Mechanical and Electrical Analysis of Strained Liner Effect in 35 nm Fully Depleted Silicon-on-Insulator Devices with Ultra Thin Silicon Channels

T. Skotnicki, R. Pantel, C. Fenouillet-Béranger, 2006 .

Bibliographie de l’auteur

D. Dutartre, S. Monfray, N. Loubet, 2014, Un nouveau référentiel pour la culture ?.

Study of model esterifications and of polyesterifications catalyzed by various organometallic derivatives—I. Study of esterifications catalyzed by titanium derivatives

F. Leverd, A. Fradet, E. Maréchal, 1987 .

Patterning of silicon nitride for CMOS gate spacer technology. III. Investigation of synchronously pulsed CH3F/O2/He plasmas

F. Leverd, R. Blanc, M. Darnon, 2014 .

Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below

O. Faynot, F. Andrieu, T. Skotnicki, 2010, 2009 Proceedings of ESSCIRC.

FDSOI devices with thin BOX and ground plane integration for 32nm node and below

X. Garros, O. Faynot, C. Laviron, 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

High-Performance High-$K$/Metal Planar Self-Aligned Gate-All-Around CMOS Devices

T. Skotnicki, F. Leverd, D. Dutartre, 2008, IEEE Transactions on Nanotechnology.

Study of model esterifications and of polyesterifications catalyzed by various organometallic derivatives—III. Kinetic and mechanistic study of eterifications catalyzed by tetrabutoxytitanium or zirconium

F. Leverd, A. Fradet, E. Maréchal, 1987 .

Emerging silicon-on-nothing (SON) devices technology

Stephane Monfray, T. Skotnicki, D. Chanemougame, 2004 .

Optical Phased Array for 905-nm LIDAR applications integrated on 300mm Si-Photonic Platform

S. Monfray, F. Leverd, F. Boeuf, 2022, Optical Fiber Communications Conference and Exhibition.

MOS Capacitor Deep Trench Isolation for CMOS image sensors

F. Leverd, F. Roy, B. Orlando, 2014, 2014 IEEE International Electron Devices Meeting.

ep Trench Isolation for CMOS Image S

Francois Roy, Bastien Mamdy, Nayera Ahmed, 2014 .

Folded fully depleted FET using Silicon-On-Nothing technology as a highly W-scaled planar solution

C. Laviron, Stephane Monfray, Claire Fenouillet-Beranger, 2009, ESSDERC 2009.

First 80 nm SON (Silicon-On-Nothing) MOSFETs with perfect morphology and high electrical performance

M. Haond, T. Skotnicki, S. Monfray, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Highly-performant 38 nm SON (silicon-on-nothing) P-MOSFETs with 9 nm-thick channels

M. Haond, T. Skotnicki, S. Monfray, 2002, 2002 IEEE International SOI Conference.

Investigation of 193-nm resist and plasma interactions during an oxide etching process

Francois Leverd, Philippe Spinelli, Benedicte P. Mortini, 2003, SPIE Advanced Lithography.

Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology

X. Garros, O. Faynot, D. Noblet, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below

T. Skotnicki, Sébastien Haendler, F. Leverd, 2009, 2009 Proceedings of the European Solid State Device Research Conference.

Trench filling with phosphorus-doped monocrystalline and polycrystalline silicon

F. Leverd, F. Deprat, A. Roman, 2022, Materials Science in Semiconductor Processing.